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NEC 78K/0S Series User Manual

8-bit single-chip microcontroller
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User's Manual
78K/0S Series
8-Bit Single-Chip Microcontroller
Instructions
Common to 78K/0S Series
Document No.
U11047EJ3V0UMJ1 (3rd edition)
Date Published November 2000 N CP(K)
©
1996
Printed in Japan

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Summary of Contents for NEC 78K/0S Series

  • Page 1 User’s Manual 78K/0S Series 8-Bit Single-Chip Microcontroller Instructions Common to 78K/0S Series Document No. U11047EJ3V0UMJ1 (3rd edition) Date Published November 2000 N CP(K) © 1996 Printed in Japan...
  • Page 2 [MEMO] User’s Manual U11047EJ3V0UM00...
  • Page 3 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
  • Page 4 NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.
  • Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 6 MAJOR REVISIONS IN THIS EDITION Page Contents Throughout • Addition of the following target products µ PD789046, 789104, 789114, 789124, 789134, 789146, 789156, 789167, 789177, 789197AY, 789217AY, 789407A, 789417A, and 789842 Subseries • Deletion of the following target products µ PD789407, 789417, and 789806Y Subseries p.
  • Page 7 → Check the mnemonic in CHAPTER 4 INSTRUCTION SET, then the functions in CHAPTER 5 EXPLANATION OF INSTRUCTIONS. • To understand the overall functions of the 78K/0S Series products instructions in general: → Read this manual in the order of the CONTENTS.
  • Page 8 • To learn the hardware functions of the 78K/0S Series products: → Refer to the user's manual for each product (see Related documents). Conventions Data significance: Higher digits on the left and lower digits on the right Footnote for item marked with Note in the text...
  • Page 9 • • • • µ µ µ µ PD789104 Subseries Document Name Document Number English Japanese µ PD789101, 789102, 789104 Data Sheet To be prepared U12815J µ PD789134 Subseries User’s Manual U13045E U13045J • • • • µ µ µ µ PD789114 Subseries Document Name Document Number English...
  • Page 10 • • • • µ µ µ µ PD789197AY Subseries Document Name Document Number English Japanese µ PD789196AY, 789197AY Preliminary Product Information U13853E U13853J µ PD78F9197Y Preliminary Product Information U13224E U13224J µ PD789217Y Subseries User’s Manual U13186E U13186J • • • • µ µ µ µ PD789217AY Subseries Document Name Document Number English...

  • Page 11: Table Of Contents

    CONTENTS CHAPTER 1 MEMORY SPACE........................ 15 Memory Space............................15 Internal Program Memory (Internal ROM) Space ................... 15 Vector Table Area ............................. 17 CALLT Instruction Table Area ......................... 20 Internal Data Memory Space........................20 Special Function Register (SFR) Area ....................22 CHAPTER 2 REGISTERS ........................
  • Page 12 CHAPTER 5 EXPLANATION OF INSTRUCTIONS.................. 57 8-Bit Data Transfer Instructions ......................59 16-Bit Data Transfer Instructions ......................62 8-Bit Operation Instructions ........................65 16-Bit Operation Instructions ........................74 Increment/Decrement Instructions......................78 Rotate Instructions ........................... 83 Bit Manipulation Instructions ........................88 CALL/RETURN Instructions........................
  • Page 13 1-9. 1-10. Vector Table (0000H to 0019H) ( µ PD789800 Subseries) ................19 1-11. Vector Table (0000H to 0023H) ( µ PD789842 Subseries) ................19 1-12. Internal Data Memory Space of 78K/0S Series Products.................20 4-1. Operand Representation and Description Formats ..................40 User’s Manual U11047EJ3V0UM00...
  • Page 14 [MEMO] User’s Manual U11047EJ3V0UM00...

  • Page 15: Chapter 1 Memory Space

    1.2 Internal Program Memory (Internal ROM) Space The 78K/0S Series product has internal ROM in the address space shown below. Program and table data, etc. are stored in ROM. This memory space is usually addressed by the program counter (PC).
  • Page 16 CHAPTER 1 MEMORY SPACE Table 1-1. Internal ROM Space of 78K/0S Series Products (2/2) Capacity 2 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes Address 0000H to 0000H to 0000H to 0000H to 0000H to...

  • Page 17: Vector Table Area

    CHAPTER 1 MEMORY SPACE 1.3 Vector Table Area The vector table area stores program start addresses to which execution branches when the RESET signal is input or when an interrupt request is generated. Of the 16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address.
  • Page 18 CHAPTER 1 MEMORY SPACE Table 1-6. Vector Table (0000H to 0019H) ( µ µ µ µ PD789146, 789156 Subseries) Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H RESET input 000EH INTST20 0004H INTWDT 0010H INTTM80 0006H INTP0 0012H INTTM20 0008H...
  • Page 19 CHAPTER 1 MEMORY SPACE Table 1-9. Vector Table (0000H to 0023H) ( µ µ µ µ PD789407A and µ µ µ µ PD789417A Subseries) Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H RESET input 0014H INTWTI 0004H INTWDT 0016H INTTM00...

  • Page 20: Callt Instruction Table Area

    The 78K/0S Series products incorporate the following data memory: (1) Internal high-speed RAM The 78K/0S Series products incorporate internal high-speed RAM in the address space shown in Table 1-12. The internal high-speed RAM is also used as a stack memory.
  • Page 21 CHAPTER 1 MEMORY SPACE Table 1-12. Internal Data Memory Space of 78K/0S Series Products (2/2) Subseries Name Product Name High-Speed RAM LCD Display RAM EEPROM µ PD789124 µ PD789121   FE00H to FEFFH µ PD789122 Subseries (256 bytes) µ PD789124 µ...

  • Page 22: Special Function Register (Sfr) Area

    CHAPTER 1 MEMORY SPACE 1.6 Special Function Register (SFR) Area Special-function registers (SFRs) of on-chip peripheral hardware are allocated to the area FF00H to FFFFH (refer to the User's Manual of each product). User’s Manual U11047EJ3V0UM00...

  • Page 23: Chapter 2 Registers

    CHAPTER 2 REGISTERS 2.1 Control Registers The control registers have dedicated functions such as controlling the program sequence, statuses, and stack memory. The control registers include a program counter, program status word, and stack pointer. 2.1.1 Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched.

  • Page 24: Stack Pointer (Sp)

    CHAPTER 2 REGISTERS (1) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, all interrupts except non-maskable interrupts are disabled (DI status). When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupt requests is controlled by the interrupt mask flag for each interrupt source.

  • Page 25: General-Purpose Registers

    CHAPTER 2 REGISTERS Figure 2-4. Data to Be Saved to Stack Memory PUSH rp CALL, CALLT Interrupt instruction instructions − − − − PC7 to PC0 Lower byte in − − − PC7 to PC0 PC15 to PC8 register pair Upper byte in −...

  • Page 26: General-Purpose Register Configuration

    CHAPTER 2 REGISTERS Figure 2-6. General-Purpose Register Configuration (a) Absolute name 16-bit processing 8-bit processing (b) Functional name 16-bit processing 8-bit processing User’s Manual U11047EJ3V0UM00...

  • Page 27: Special Function Registers (Sfrs)

    CHAPTER 2 REGISTERS 2.3 Special Function Registers (SFRs) Unlike general-purpose registers, special function registers have their own functions and are allocated to the 256- byte area FF00H to FFFFH. A special function register can be manipulated, like a general-purpose register, by using operation, transfer, and bit manipulation instructions.
  • Page 28 [MEMO] User’s Manual U11047EJ3V0UM00...

  • Page 29: Chapter 3 Addressing

    CHAPTER 3 ADDRESSING 3.1 Addressing of Instruction Address An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 per byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.

  • Page 30: Immediate Addressing

    CHAPTER 3 ADDRESSING 3.1.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and program branches. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. The CALL !addr16 and BR !addr16 instructions can be used to branch to any address within the memory spaces.

  • Page 31: Table Indirect Addressing

    CHAPTER 3 ADDRESSING 3.1.3 Table indirect addressing [Function] Table contents (branch destination address) of a particular location, addressed by the immediate data of bits 1 to 5 of an instruction code are transferred to the program counter (PC), and program branches. Table indirect addressing is performed when the CALLT [addr5] instruction is executed.

  • Page 32: Register Addressing

    CHAPTER 3 ADDRESSING 3.1.4 Register addressing [Function] Register pair (AX) contents specified with an instruction word are transferred to the program counter (PC) and program branches. This function is carried out when the BR AX instruction is executed. [Illustration] User’s Manual U11047EJ3V0UM00...

  • Page 33: Addressing Of Operand Address

    CHAPTER 3 ADDRESSING 3.2 Addressing of Operand Address The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.2.1 Direct addressing [Function] This addressing directly addresses a memory to be manipulated with immediate data in an instruction word. [Operand format] Operand Description...

  • Page 34: Short Direct Addressing

    CHAPTER 3 ADDRESSING 3.2.2 Short direct addressing [Function] This addressing directly addresses memory to be manipulated in the fixed space with the 8-bit data in an instruction word. This addressing is applied to the 256-byte fixed space of FE20H to FF1FH. An internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

  • Page 35: Special Function Register (Sfr) Addressing

    CHAPTER 3 ADDRESSING 3.2.3 Special function register (SFR) addressing [Function] This addressing is to address special function registers (SFRs) mapped to the memory with the 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces of FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can also be accessed by means of short direct addressing.

  • Page 36: Register Addressing

    CHAPTER 3 ADDRESSING 3.2.4 Register addressing [Function] This addressing is to access a general-purpose register by specifying it as an operand. The general-purpose register to be accessed is specified with a register specification code in an instruction code or function name. Register addressing is carried out when an instruction with the following operand format is executed.

  • Page 37: Register Indirect Addressing

    CHAPTER 3 ADDRESSING 3.2.5 Register indirect addressing [Function] This addressing is to address memory using the contents of the special register pair as an operand. The register pair to be accessed is specified with the register pair specification code in an instruction code. This addressing can be carried out for the entire memory space.

  • Page 38: Based Addressing

    CHAPTER 3 ADDRESSING 3.2.6 Based addressing [Function] This addressing is to address the memory by using the result of adding 8-bit immediate data to the contents of the base register, i.e., the HL register pair. The addition is performed by expanding the offset data as a positive number to 16 bits.

  • Page 39: Chapter 4 Instruction Set

    CHAPTER 4 INSTRUCTION SET This chapter lists the instruction set of the 78K/0S Series. The instructions are common to all 78K/0S Series products. User’s Manual U11047EJ3V0UM00...

  • Page 40: Operation

    CHAPTER 4 INSTRUCTION SET 4.1 Operation 4.1.1 Operand representation and description formats In the operand column of each instruction, an operand is described according to the description format for operand representation of that instruction (for details, refer to the assembler specifications). When there are two or more description methods, select one of them.

  • Page 41: Description Of Operation Column

    CHAPTER 4 INSTRUCTION SET 4.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...

  • Page 42: Description Of Clock Column

    CHAPTER 4 INSTRUCTION SET 4.1.4 Description of clock column The number of clock cycles during instruction execution is outlined as follows. One instruction clock cycle is equal to one CPU clock cycle (f ) selected by the processor clock control register (PCC).

  • Page 43: Operation List

    CHAPTER 4 INSTRUCTION SET 4.1.5 Operation list Mnemonic Operand Byte Clock Operation Flag AC CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte A ← r Note 1 A, r r ← A Note 1 r, A A ←...
  • Page 44 CHAPTER 4 INSTRUCTION SET Mnemonic Operand Byte Clock Operation Flag AC CY rp ← word MOVW rp, #word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX AX ← rp Note AX, rp rp ← AX Note rp, AX AX ↔...
  • Page 45 CHAPTER 4 INSTRUCTION SET Mnemonic Operand Byte Clock Operation Flag AC CY A, CY ← A – byte – CY × × × SUBC A, #byte (saddr), CY ← (saddr) – byte – CY × × × saddr, #byte A, CY ← A – r – CY ×...
  • Page 46 CHAPTER 4 INSTRUCTION SET Mnemonic Operand Byte Clock Operation Flag AC CY AX, CY ← AX + word × × × ADDW AX, #word AX, CY ← AX – word × × × SUBW AX, #word × × × CMPW AX, #word AX –...
  • Page 47 CHAPTER 4 INSTRUCTION SET Mnemonic Operand Byte Clock Operation Flag AC CY ← (SP + 1), PC ← (SP), SP ← SP + 2 ← (SP + 1), PC ← (SP), RETI PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0 (SP –...

  • Page 48: Instruction List By Addressing

    CHAPTER 4 INSTRUCTION SET 4.1.6 Instruction list by addressing (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd operand [DE] [HL] None #byte saddr !addr16 $addr16 [HL + byte] 1st operand Note...
  • Page 49 CHAPTER 4 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd operand #word saddrp None 1st operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, HL.
  • Page 50 CHAPTER 4 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, DBNZ 2nd operand !addr16 [addr5] $addr16 1st operand Basic instructions CALL CALLT Compound instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U11047EJ3V0UM00...

  • Page 51: Instruction Codes

    CHAPTER 4 INSTRUCTION SET 4.2 Instruction Codes 4.2.1 Description of instruction code table reg-pair Immediate data corresponding to “bit” Data: 8-bit immediate data corresponding to “byte” Low/High byte: 16-bit immediate data corresponding to “word” Saddr-offset: 16-bit address lower 8-bit offset data corresponding to “saddr” Sfr-offset: sfr 16-bit address lower 8-bit offset data Low/High addr: 16-bit immediate data corresponding to “addr16”...

  • Page 52: Instruction Code List

    CHAPTER 4 INSTRUCTION SET 4.2.2 Instruction code list Mnemonic Operand Instruction Code r, #byte 0 0 0 0 1 0 1 0 1 1 1 1 R Data saddr, #byte 1 1 1 1 0 1 0 1 Saddr-offset Data sfr, #byte 1 1 1 1 0 1 1 1 Sfr-offset...
  • Page 53 CHAPTER 4 INSTRUCTION SET Mnemonic Operand Instruction Code A, #byte 1 0 0 0 0 0 1 1 Data saddr, #byte 1 0 0 0 0 0 0 1 Saddr-offset Data A, r 0 0 0 0 1 0 1 0 1 0 0 0 R A, saddr 1 0 0 0 0 1 0 1...
  • Page 54 CHAPTER 4 INSTRUCTION SET Mnemonic Operand Instruction Code A, #byte 0 1 1 1 0 0 1 1 Data saddr, #byte 0 1 1 1 0 0 0 1 Saddr-offset Data A, r 0 0 0 0 1 0 1 0 0 1 1 1 R A, saddr 0 1 1 1 0 1 0 1...
  • Page 55 CHAPTER 4 INSTRUCTION SET Mnemonic Operand Instruction Code SET1 saddr.bit 0 0 0 0 1 0 1 0 1 0 1 0 Saddr-offset sfr.bit 0 0 0 0 1 0 1 0 0 1 1 0 Sfr-offset A.bit 0 0 0 0 1 0 1 0 0 0 1 0 PSW.bit 0 0 0 0 1 0 1 0...
  • Page 56 CHAPTER 4 INSTRUCTION SET Mnemonic Operand Instruction Code saddr.bit, $addr16 0 0 0 0 1 0 1 0 1 0 0 0 Saddr-offset jdisp sfr.bit, $addr16 0 0 0 0 1 0 1 0 0 1 0 0 Sfr-offset jdisp A.bit, $addr16 0 0 0 0 1 0 1 0 0 0 0 0...

  • Page 57: Chapter 5 Explanation Of Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS This chapter explains the instructions of 78K/0S Series. Each instruction is described in the unit of mnemonic, including description of multiple operands. The basic configuration of instruction descriptions is shown on the next page. For the number of instruction bytes and operation codes, refer to CHAPTER 4 INSTRUCTION SET.
  • Page 58 CHAPTER 5 EXPLANATION OF INSTRUCTIONS DESCRIPTION EXAMPLE Mnemonic Full name Move Byte Data Transfer Meaning of instruction [Instruction format] MOV dst, src: Indicates the basic description format of the instruction. dst ← src: Indicates instruction operation using symbols. [Operation] [Operand] Indicates operands that can be specified with this instruction.

  • Page 59: 8-Bit Data Transfer Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.1 8-Bit Data Transfer Instructions The following instructions are 8-bit data transfer instructions. MOV ... 60 XCH ... 61 User’s Manual U11047EJ3V0UM00...
  • Page 60 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Move Byte Data Transfer [Instruction format] MOV dst, src dst ← src [Operation] [Operand] Mnemonic Operand (dst, src) Mnemonic Operand (dst, src) r, #byte !addr16, A saddr, #byte PSW, #byte sfr, #byte A, PSW Note A, r PSW, A Note...
  • Page 61 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Exchange Byte Data Exchange [Instruction format] XCH dst, src dst ↔ src [Operation] [Operand] Mnemonic Operand (dst, src) A, X Note A, r A, saddr A, sfr A, [DE] A, [HL] A, [HL + byte] Note Except r = A, X [Flag] [Description]...

  • Page 62: 16-Bit Data Transfer Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.2 16-Bit Data Transfer Instructions The following instructions are 16-bit data transfer instructions. MOVW ... 63 XCHW ... 64 User’s Manual U11047EJ3V0UM00...
  • Page 63 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Move Word MOVW Word Data Transfer [Instruction format] MOVW dst, src dst ← src [Operation] [Operand] Mnemonic Operand (dst, src) MOVW rp, #word AX, saddrp saddrp, AX Note AX, rp Note rp, AX Note Only when rp = BC, DE or HL [Flag] [Description] •...
  • Page 64 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Exchange Word XCHW Word Data Exchange [Instruction format] XCHW dst, src dst ↔ src [Operation] [Operand] Mnemonic Operand (dst, src) Note XCHW AX, rp Note Only when rp = BC, DE or HL [Flag] [Description] •...

  • Page 65: 8-Bit Operation Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.3 8-Bit Operation Instructions The following are 8-bit operation instructions. ADD ... 66 ADDC ... 67 SUB ... 68 SUBC ... 69 AND ... 70 OR ... 71 XOR ... 72 CMP ... 73 User’s Manual U11047EJ3V0UM00...
  • Page 66 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Byte Data Addition [Instruction format] ADD dst, src dst, CY ← dst + src [Operation] [Operand] Mnemonic Operand (dst, src) Mnemonic Operand (dst, src) A, #byte A, !addr16 saddr, #byte A, [HL] A, r A, [HL + byte] A, saddr [Flag] ×...
  • Page 67 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Add with Carry ADDC Addition of Byte Data with Carry [Instruction format] ADDC dst, src dst, CY ← dst + src + CY [Operation] [Operand] Mnemonic Operand (dst, src) Mnemonic Operand (dst, src) ADDC A, #byte ADDC A, !addr16 saddr, #byte...
  • Page 68 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Subtract Byte Data Subtraction [Instruction format] SUB dst, src dst, CY ← dst – src [Operation] [Operand] Mnemonic Operand (dst, src) Mnemonic Operand (dst, src) A, #byte A, !addr16 saddr, #byte A, [HL] A, r A, [HL + byte] A, saddr [Flag]...
  • Page 69 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Subtract with Carry SUBC Subtraction of Byte Data with Carry [Instruction format] SUBC dst, src dst, CY ← dst – src – CY [Operation] [Operand] Mnemonic Operand (dst, src) Mnemonic Operand (dst, src) SUBC A, #byte SUBC A, !addr16 saddr, #byte...
  • Page 70 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Logical Product of Byte Data [Instruction format] AND dst, src dst ← dst ∧ src [Operation] [Operand] Mnemonic Operand (dst, src) Mnemonic Operand (dst, src) A, #byte A, !addr16 saddr, #byte A, [HL] A, r A, [HL + byte] A, saddr [Flag]...
  • Page 71 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Logical Sum of Byte Data [Instruction format] OR dst, src dst ← dst ∨ src [Operation] [Operand] Mnemonic Operand (dst, src) Mnemonic Operand (dst, src) A, #byte A, !addr16 saddr, #byte A, [HL] A, r A, [HL + byte] A, saddr [Flag]...
  • Page 72 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Exclusive Or Exclusive Logical Sum of Byte Data [Instruction format] XOR dst, src dst ← dst ∨ src [Operation] [Operand] Mnemonic Operand (dst, src) Mnemonic Operand (dst, src) A, #byte A, !addr16 saddr, #byte A, [HL] A, r A, [HL + byte] A, saddr...
  • Page 73 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Compare Byte Data Comparison [Instruction format] CMP dst, src [Operation] dst – src [Operand] Mnemonic Operand (dst, src) Mnemonic Operand (dst, src) A, #byte A, !addr16 saddr, #byte A, [HL] A, r A, [HL + byte] A, saddr [Flag] ×...

  • Page 74: 16-Bit Operation Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.4 16-Bit Operation Instructions The following are 16-bit operation instructions. ADDW ... 75 SUBW ... 76 CMPW ... 77 User’s Manual U11047EJ3V0UM00...
  • Page 75 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Add Word ADDW Word Data Addition [Instruction format] ADDW dst, src dst, CY ← dst + src [Operation] [Operand] Mnemonic Operand (dst, src) ADDW AX, #word [Flag] × × × [Description] • The destination operand (dst) specified with the 1st operand is added to the source operand (src) specified with the 2nd operand and the result is stored in the destination operand (dst).
  • Page 76 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Subtract Word SUBW Word Data Subtraction [Instruction format] SUBW dst, src dst, CY ← dst – src [Operation] [Operand] Mnemonic Operand (dst, src) SUBW AX, #word [Flag] × × × [Description] • The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst) specified with the 1st operand and the result is stored in the destination operand (dst) and the CY flag.
  • Page 77 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Compare Word CMPW Word Data Comparison [Instruction format] CMPW dst, src [Operation] dst – src [Operand] Mnemonic Operand (dst, src) CMPW AX, #word [Flag] × × × [Description] • The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst) specified with the 1st operand.

  • Page 78: Increment/Decrement Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.5 Increment/Decrement Instructions The following are increment/decrement instructions. INC ... 79 DEC ... 80 INCW ... 81 DECW ... 82 User’s Manual U11047EJ3V0UM00...
  • Page 79 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Increment Byte Data Increment [Instruction format] INC dst dst ← dst + 1 [Operation] [Operand] Mnemonic Operand (dst) saddr [Flag] × × [Description] • The destination operand (dst) contents are incremented by only one. • If the increment result is 0, the Z flag is set (1).
  • Page 80 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement Byte Data Decrement [Instruction format] DEC dst dst ← dst – 1 [Operation] [Operand] Mnemonic Operand (dst) saddr [Flag] × × [Description] • The destination operand (dst) contents are decremented by only one. • If the decrement result is 0, the Z flag is set (1).
  • Page 81 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Increment Word INCW Word Data Increment [Instruction format] INCW dst dst ← dst + 1 [Operation] [Operand] Mnemonic Operand (dst) INCW [Flag] [Description] • The destination operand (dst) contents are incremented by only one. • Because this instruction is frequently used for increment of a register (pointer) used for addressing, the Z, AC, and CY flag contents are not changed.
  • Page 82 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement Word DECW Word Data Decrement [Instruction format] DECW dst dst ← dst – 1 [Operation] [Operand] Mnemonic Operand (dst) DECW [Flag] [Description] • The destination operand (dst) contents are decremented by only one. • Because this instruction is frequently used for decrement of a register (pointer) used for addressing, the Z, AC, and CY flag contents are not changed.

  • Page 83: Rotate Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.6 Rotate Instructions The following are rotate instructions. ROR ... 84 ROL ... 85 RORC ... 86 ROLC ... 87 User’s Manual U11047EJ3V0UM00...
  • Page 84 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Right Byte Data Rotation to the Right [Instruction format] ROR dst, cnt ← dst ← dst ) × one time [Operation] (CY, dst , dst m–1 [Operand] Mnemonic Operand (dst, cnt) A, 1 [Flag] ×...
  • Page 85 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Left Byte Data Rotation to the Left [Instruction format] ROL dst, cnt ← 0dst ← dst ) × one time [Operation] (CY, dst , dst [Operand] Mnemonic Operand (dst, cnt) A, 1 [Flag] × [Description] •...
  • Page 86 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Right with Carry RORC Byte Data Rotation to the Right with Carry [Instruction format] RORC dst, cnt (CY ← dst ← CY, dst ← dst ) × one time [Operation] , dst m–1 [Operand] Mnemonic Operand (dst, cnt) RORC...
  • Page 87 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Left with Carry ROLC Byte Data Rotation to the Left with Carry [Instruction format] ROLC dst, cnt (CY ← dst ← CY, dst ← dst ) × one time [Operation] , dst [Operand] Mnemonic Operand (dst, cnt) ROLC A, 1...

  • Page 88: Bit Manipulation Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.7 Bit Manipulation Instructions The following are bit manipulation instructions. SET1 ... 89 CLR1 ... 90 NOT1 ... 91 User’s Manual U11047EJ3V0UM00...
  • Page 89 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Set Single Bit (Carry Flag) SET1 1 Bit Data Set [Instruction format] SET1 dst dst ← 1 [Operation] [Operand] Mnemonic Operand (dst) SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit [Flag] dst = PSW.bit dst = CY In all other cases ×...
  • Page 90 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Clear Single Bit (Carry Flag) CLR1 1 Bit Data Clear [Instruction format] CLR1 dst dst ← 0 [Operation] [Operand] Mnemonic Operand (dst) CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit [Flag] dst = PSW.bit dst = CY In all other cases ×...
  • Page 91 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Not Single Bit (Carry Flag) NOT1 1 Bit Data Logical Negation [Instruction format] NOT1 dst _______ dst ← [Operation] [Operand] Mnemonic Operand (dst) NOT1 [Flag] × [Description] • The CY flag is inverted. [Description example] NOT1 CY;...

  • Page 92: Call/Return Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.8 CALL/RETURN Instructions The following are call/return instructions. CALL ... 93 CALLT ... 94 RET ... 95 RETI ... 96 User’s Manual U11047EJ3V0UM00...
  • Page 93 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Call CALL Subroutine Call (16 Bit Direct) [Instruction format] CALL target (SP – 1) ← (PC + 3) [Operation] (SP – 2) ← (PC + 3) ← SP – 2, ← target [Operand] Mnemonic Operand (target) CALL !addr16 [Flag]...
  • Page 94 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Call Table CALLT Subroutine Call (Call Table Reference) [Instruction format] CALLT [addr5] (SP – 1) ← (PC + 1) [Operation] (SP – 2) ← (PC + 1) ← SP – 2, ← (00000000,addr5 + 1) ←...
  • Page 95 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Return Return from Subroutine [Instruction format] ← (SP), [Operation] ← (SP + 1), SP ← SP + 2 [Operand] None [Flag] [Description] • This is a return instruction from the subroutine call made with the CALL and CALLT instructions. •...
  • Page 96 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Return from Interrupt RETI Return from Hardware Vectored Interrupt [Instruction format] RETI ← (SP), [Operation] ← (SP + 1), PSW ← (SP + 2), ← SP + 3, NMIS ← 0 [Operand] None [Flag] [Description] •...

  • Page 97: Stack Manipulation Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.9 Stack Manipulation Instructions The following are stack manipulation instructions. PUSH ... 98 POP ... 99 MOVW SP, AX ... 100 MOVW AX, SP ... 100 User’s Manual U11047EJ3V0UM00...
  • Page 98 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Push PUSH Push [Instruction format] PUSH src [Operation] When src = rp When src = PSW (SP – 1) ← src (SP – 1) ← src (SP – 2) ← src ← SP − 1 ←SP −...
  • Page 99 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] POP dst [Operation] When dst = rp When dst = PSW ← (SP), dst ← (SP) ← (SP + 1), SP ← SP + 1 ← SP + 2 [Operand] Mnemonic Operand (dst) [Flag] dst = rp [Description]...
  • Page 100 CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOVW SP, AX Move Word Word Data Transfer with Stack Pointer MOVW AX, SP MOVW dst, src [Instruction format] dst ← src [Operation] [Operand] Mnemonic Operand (dst, src) MOVW SP, AX AX, SP [Flag] [Description] •...

  • Page 101: Unconditional Branch Instruction

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.10 Unconditional Branch Instruction The following is an unconditional branch instruction. BR ... 102 User’s Manual U11047EJ3V0UM00...
  • Page 102 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch Unconditional Branch [Instruction format] BR target PC ← target [Operation] [Operand] Mnemonic Operand (target) !addr16 $addr16 [Flag] [Description] • This is an instruction to branch unconditionally. • The word data of the target address operand (target) is transferred to PC and program branches. [Description example] BR AX;...

  • Page 103: Conditional Branch Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.11 Conditional Branch Instructions The following are conditional branch instructions. BC ... 104 BNC ... 105 BZ ... 106 BNZ ... 107 BT ... 108 BF ... 109 DBNZ ... 110 User’s Manual U11047EJ3V0UM00...
  • Page 104 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Carry Conditional Branch with Carry Flag (CY = 1) [Instruction format] BC $addr16 PC ← PC + 2 + jdisp8 if CY = 1 [Operation] [Operand] Mnemonic Operand ($addr16) $addr16 [Flag] [Description] • When CY = 1, program branches to the address specified with the operand.
  • Page 105 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Not Carry Conditional Branch with Carry Flag (CY = 0) [Instruction format] BNC $addr16 PC ← PC + 2 + jdisp8 if CY = 0 [Operation] [Operand] Mnemonic Operand ($addr16) $addr16 [Flag] [Description] •...
  • Page 106 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Zero Conditional Branch with Zero Flag (Z = 1) [Instruction format] BZ $addr16 PC ← PC + 2 + jdisp8 if Z = 1 [Operation] [Operand] Mnemonic Operand ($addr16) $addr16 [Flag] [Description] • When Z = 1, program branches to the address specified with the operand.
  • Page 107 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Not Zero Conditional Branch with Zero Flag (Z = 0) [Instruction format] BNZ $addr16 PC ← PC + 2 + jdisp8 if Z = 0 [Operation] [Operand] Mnemonic Operand ($addr16) $addr16 [Flag] [Description] •...
  • Page 108 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if True Conditional Branch by Bit Test (Byte Data Bit = 1) [Instruction format] BT bit, $addr16 PC ← PC + b + jdisp8 if bit = 1 [Operation] [Operand] Mnemonic Operand (bit, $addr16) b (Number of bytes) saddr.bit, $addr16 sfr.bit, $addr16...
  • Page 109 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if False Conditional Branch by Bit Test (Byte Data Bit = 0) [Instruction format] BF bit, $addr16 PC ← PC + b + jdisp8 if bit = 0 [Operation] [Operand] Mnemonic Operand (bit, $addr16) b (Number of bytes) saddr.bit, $addr16 sfr.bit, $addr16...
  • Page 110 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement and Branch if Not Zero DBNZ Conditional Loop (R1 ≠ ≠ ≠ ≠ 0) [Instruction format] DBNZ dst, $addr16 dst ← dst – 1, [Operation] then PC ← PC + b + jdisp16 if dst R1 ≠ 0 [Operand] Mnemonic Operand (dst, $addr16)

  • Page 111: Cpu Control Instructions

    CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.12 CPU Control Instructions The following are CPU control instructions. NOP ... 112 EI ... 113 DI ... 114 HALT ... 115 STOP ... 116 User’s Manual U11047EJ3V0UM00...
  • Page 112 CHAPTER 5 EXPLANATION OF INSTRUCTIONS No Operation No Operation [Instruction format] [Operation] no operation [Operand] None [Flag] [Description] • No processing is performed and only time is consumed. User’s Manual U11047EJ3V0UM00...
  • Page 113 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Enable Interrupt Interrupt Enabled [Instruction format] IE ← 1 [Operation] [Operand] None [Flag] [Description] • The maskable interrupt acknowledge-enable status is set (by setting the interrupt enable flag (IE) (1)). • Interrupts are acknowledged immediately after this instruction is executed. •...
  • Page 114 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Disable Interrupt Interrupt Disabled [Instruction format] IE ← 0 [Operation] [Operand] None [Flag] [Description] • Maskable interrupt acknowledgment with vectored interrupt is disabled (with the interrupt enable flag (IE) cleared (0)). • No interrupts are acknowledged between this instruction and the subsequent instruction. •...
  • Page 115 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Halt HALT HALT Mode Set [Instruction format] HALT [Operation] Set HALT Mode [Operand] None [Flag] [Description] • This instruction is used to set the HALT mode to stop the CPU operation clock. Total power consumption of the system can be reduced with intermittent operations through combination with the normal operation mode.
  • Page 116 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Stop STOP Stop Mode Set [Instruction format] STOP [Operation] Set STOP Mode [Operand] None [Flag] [Description] • This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole system.

  • Page 117: Appendix A Instruction Index (Mnemonic: By Function)

    APPENDIX A INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) [8-bit data transfer instructions] [Bit manipulation instructions] MOV ... 60 SET1 ... 89 XCH ... 61 CLR1 ... 90 NOT1 ... 91 [16-bit data transfer instructions] [Call/return instructions] MOVW ... 63 XCHW ... 64 CALL ...
  • Page 118 [MEMO] User’s Manual U11047EJ3V0UM00...

  • Page 119: Appendix B Instruction Index (Mnemonic: In Alphabetical Order)

    APPENDIX B INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) ADD ... 66 MOV ... 60 ADDC ... 67 MOVW ... 63 ADDW ... 75 MOVW AX, SP ... 100 AND ... 70 MOVW SP, AX ... 100 BC ... 104 NOP ... 112 BF ...
  • Page 120 [MEMO] User’s Manual U11047EJ3V0UM00...

  • Page 121: Appendix C Revision History

    µ PD789026, 789407, 789417, 789800, and 789806Y Subseries Modification of the format of the table of the internal data memory space of the CHAPTER 1 MEMORY SPACE 78K/0S Series products Addition of the following target products Throughout µ PD789046, 789104, 789114, 789124, 789134, 789146, 789156, 789167,...
  • Page 122 [MEMO] User’s Manual U11047EJ3V0UM00...
  • Page 123 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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