NEC 78K0 Series User Manual page 302

Figure 12-2. Format of Clock Output Selection Register (CKS)
Address: FF40H After reset: 00H
Symbol <7>
CKS BZOE
BZOE
0
1
BCS1
0
0
1
1
CLOE
0
1
CCS3
0
0
0
0
0
0
0
0
1
If the peripheral hardware clock operates on the internal high-speed oscillation clock when 1.8 V ≤ V
Notes 1.
< 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: f
2. The PCL output clock prohibits settings if they exceed 10 MHz.
Cautions 1. Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0).
2. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
Remarks 1. f : Peripheral hardware clock frequency
PRS
2. f : Subsystem clock frequency
SUB
302
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R/W
6 5
BCS1 BCS0
BUZ output enable/disable specification
Clock division circuit operation stopped. BUZ fixed to low level.
Clock division circuit operation enabled. BUZ output enabled.
BCS0
10
0 f /2
PRS
11
1 f /2
PRS
12
0 f /2
PRS
13
1 f /2
PRS
PCL output enable/disable specification
Clock division circuit operation stopped. PCL fixed to low level.
Clock division circuit operation enabled. PCL output enabled.
CCS2 CCS1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
Other than above
Preliminary User's Manual U17260EJ3V1UD
<4> 3 2
CLOE CCS3 CCS2
BUZ output clock selection
f = 10 MHz
PRS
9.77 kHz
4.88 kHz
2.44 kHz
1.22 kHz
CCS0 PCL output clock selection
f =
SUB
32.768 kHz
−
Note 1
0 f
PRS
1 f /2
PRS
2
0 f /2
PRS
3
1 f /2
PRS
4
0 f /2
PRS
5
1 f /2
PRS
6
0 f /2
PRS
7
1 f /2
PRS
0 f 32.768 kHz
SUB
Setting prohibited
1 0
CCS1 CCS0
f = 20 MHz
PRS
19.54 kHz
9.77 kHz
4.88 kHz
2.44 kHz
f = f =
PRS PRS
10 MHz 20 MHz
10 MHz Setting
Note 2
prohibited
5 MHz 10 MHz
2.5 MHz 5 MHz
1.25 MHz 2.5 MHz
625 kHz 1.25 MHz
312.5 kHz 625 kHz
156.25 kHz 312.5 kHz
78.125 kHz 156.25 kHz
−
) is prohibited.
PRS
DD