NEC 78K0 Series User Manual page 543

Figure 24-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
Supply voltage (V )
DD
V
LVI
2.7 V (TYP.)
V = 1.59 V (TYP.)
POC
LVIMK flag
Note 1
H
(set by software)
LVISEL flag
(set by software)
L
<2>
LVION flag
(set by software)
LVIF flag
LVIMD flag
(set by software)
Note 3
LVIRF flag
LVI reset signal
POC reset signal
Internal reset signal
Notes 1. The LVIMK flag is set to "1" by reset signal generation.
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22
RESET FUNCTION.
Remark <1> to <7> in Figure 24-5 above correspond to <1> to <7> in the description of "When starting
operation" in 24.4.1 (1) When detecting level of supply voltage (V
CHAPTER 24 LOW-VOLTAGE DETECTOR
(Detects Level of Supply Voltage (V
<1>
<3>
Not cleared
<4>
<5> Wait time
<6>
Note 2
Not cleared
<7>
Cleared by
software
Preliminary User's Manual U17260EJ3V1UD
)) (2/2)
DD
Not cleared
Not cleared
Cleared by
software
).
DD
Time
Clear
Clear
Clear
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