NEC 78K0 Series User Manual page 164

Table 6-5. CPU Clock Transition and SFR Register Setting Examples (3/4)
(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) → (B)
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) → (D) (XT1 clock)
(C) → (D) (external subsystem clock)
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(D) → (B)
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
2. MCM0:
EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL)
RSTS, RSTOP:
XTSTART, CSS:
×:
164
CHAPTER 6 CLOCK GENERATOR
RSTOP
0
Unnecessary if the CPU is operating
with the internal high-speed oscillation clock
XTSTART EXCLKS
0
1
0
Unnecessary if the CPU is operating
with the subsystem clock
RSTOP
0
Unnecessary if the CPU is operating
with the internal high-speed
oscillation clock
Bit 0 of the main clock mode register (MCM)
Bits 7 and 0 of the internal oscillation mode register (RCM)
Bits 6 and 4 of the processor clock control register (PCC)
Don't care
Preliminary User's Manual U17260EJ3V1UD
RSTS
Confirm this flag is 1.
OSCSELS Waiting for
Oscillation
Stabilization
0 1 Necessary
× ×
1 1 Unnecessary
RSTS MCM0
Confirm this flag 0
is 1.
↑
Unnecessary if
XSEL is 0
MCM0
0
CSS
1
1
CSS
0