Operation List - NEC 78K0 Series User Manual

28.2 Operation List

Instruction
Mnemonic
Group
8-bit data MOV r, #byte
transfer
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
XCH A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
2. This clock cycle applies to the internal ROM program.
582
CHAPTER 28 INSTRUCTION SET
Clocks
Operands Bytes
Note 1
2 4
3 6
−
3
Note 3
1 2
Note 3
1 2
2 4
2 4
−
2
−
2
3 8
3 8
−
3
−
2
−
2
1 4
1 4
1 4
1 4
2 8
2 8
1 6
1 6
1 6
1 6
Note 3
1 2
2 4
−
2
3 8
1 4
1 4
2 8
2 8
2 8
Preliminary User's Manual U17260EJ3V1UD
Operation
Note 2
− r ← byte
(saddr) ← byte
7
sfr ← byte
7
A ← r
−
− r ← A
A ← (saddr)
5
(saddr) ← A
5
A ← sfr
5
sfr ← A
5
A ← (addr16)
9
(addr16) ← A
9
PSW ← byte
7
A ← PSW
5
PSW ← A
5
A ← (DE)
5
(DE) ← A
5
A ← (HL)
5
(HL) ← A
5
A ← (HL + byte)
9
(HL + byte) ← A
9
A ← (HL + B)
7
(HL + B) ← A
7
A ← (HL + C)
7
(HL + C) ← A
7
− A ↔ r
A ↔ (saddr)
6
A ↔ (sfr)
6
A ↔ (addr16)
10
A ↔ (DE)
6
A ↔ (HL)
6
A ↔ (HL + byte)
10
A ↔ (HL + B)
10
A ↔ (HL + C)
10
) selected by the processor clock
CPU
Flag
Z AC CY
× × ×
× × ×