NEC 78K0 Series User Manual page 310

Figure 13-5. A/D Converter Sampling and A/D Conversion Timing
←
ADCS 1 or ADS rewrite
ADCS
Sampling
timing
INTAD
Wait
period
Note For details of wait period, see CHAPTER 31 CAUTIONS FOR WAIT.
(2) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8
bits of the conversion result are stored in FF09H and the lower 2 bits are stored in the higher 2 bits of FF08H.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0000H.
Figure 13-6. Format of 10-Bit A/D Conversion Result Register (ADCR)
Address: FF08H, FF09H
Symbol
ADCR
Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may
become undefined.
writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect
conversion result to be read.
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 31 CAUTIONS FOR WAIT.
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CHAPTER 13 A/D CONVERTER
SAR Sampling time
Note
clear
Conversion time
After reset: 0000H R
FF09H
Read the conversion result following conversion completion before
Preliminary User's Manual U17260EJ3V1UD
Successive
Transfer SAR
conversion time
to ADCR, clear
INTAD
generation
0 0
Sampling time
Conversion time
FF08H
0 0 0 0