NEC 78K0 Series User Manual page 215

CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-40. Timing Example of Free-Running Timer Mode
• TOC0n = 13H, PRM0n = 10H, CRC0n = 04H, TMC0n = 04H
FFFFH
TM0n register
0000H
Operable bits
00
(TMC0n3, TMC0n2)
Capture trigger input
(TI00n)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Capture interrupt
(INTTM01n)
TO0n pin output
Overflow flag
(OVF0n)
This is an application example where a compare register and a capture register are used at the same time in the
free-running timer mode.
In this example, the INTTM00n signal is generated and the output level of the TO0n pin is reversed each time the
count value of TM0n matches the set value of CR00n (compare register). In addition, the INTTM01n signal is
generated and the count value of TM0n is captured to CR01n each time the valid edge of the TI00n pin is
detected.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
(CR00n: Compare Register, CR01n: Capture Register)
M
01
0001H
0000H M
0 write clear
Preliminary User's Manual U17260EJ3V1UD
N
S
N
0 write clear
P
Q
S Q
P
0 write clear 0 write clear
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