NEC 78K0 Series User Manual page 173

The count value of TM0n can be read by reading TM0n when the value of bits 3 and 2 (TMC0n3 and TMC0n2) of
16-bit timer mode control register 0n (TMC0n) is other than 00. The value of TM0n is 0000H if it is read when
TMC0n3 and TMC0n2 = 00.
The count value is reset to 0000H in the following cases.
• At reset signal generation
• If TMC0n3 and TMC0n2 are cleared to 00
• If the valid edge of the TI00n pin is input in the mode in which the clear & start occurs when inputting the valid
edge to the TI00n pin
• If TM0n and CR00n match in the mode in which the clear & start occurs when TM0n and CR00n match
• OSPT0n is set to 1 in one-shot pulse output mode or the valid edge is input to the TI00n pin
Cautions 1. Even if TM0n is read, the value is not captured by CR01n.
2. When TM0n is read, input of the count clock is temporarily stopped and it is resumed after
the timer has been read. Therefore, no clock miss occurs.
(2) 16-bit timer capture/compare register 00n (CR00n)), 16-bit timer capture/compare register 01n (CR01n)
CR00n and CR01n are 16-bit registers that are used with a capture function or comparison function selected by
using CRC0n.
Change the value of CR00n while the timer is stopped (TMC0n3 and TMC0n2 = 00).
The value of CR01n can be changed during operation if the value has been set in a specific way. For details, see
7.5.1 Rewriting CR01n during TM0n operation.
These registers can be read or written in 16-bit units.
Reset signal generation sets these registers to 0000H.
Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n)
Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001)
15
CR00n
(n = 0, 1)
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
FF13H (CR000), FFB3H (CR001)
14 13 12 11 10
Preliminary User's Manual U17260EJ3V1UD
After reset: 0000H
FF12H (CR000), FFB2H (CR001)
9 8 7 6 5 4
R/W
3 2 1 0
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