NEC 78K0 Series User Manual page 640

8-bit single-chip microcontrollers
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pp. 401, 402
Addition of (b) Type 3: CKP1n = 1, DAP1n = 0 and (d) Type 4: CKP1n = 1, DAP1n = 1 to Figure 16-11
Output Operation of First Bit
pp. 403, 404
Addition of (b) Type 3: CKP1n = 1, DAP1n = 0 and (d) Type 4: CKP1n = 1, DAP1n = 1 in Figure 16-12
Output Value of SO1n Pin (Last Bit)
CHAPTER 17 SERIAL INTERFACE IIC0
p. 407
Modification of Figure 17-1 Block Diagram of Serial Interface IIC0
p. 409
Addition of Caution 2 to 17.2 (1) IIC shift register 0 (IIC0) and addition to description in (2) Slave address
register 0 (SVA0)
p. 410
Addition of 17.2 (13) Stop condition generator
p. 413
Addition of description to IICE0 and addition of Caution to Figure 17-5 Format of IIC Control Register 0
(IICC0) (1/4)
p. 414
Addition of Note 2 to Figure 17-5 Format of IIC Control Register 0 (IICC0) (2/4)
p. 415
Addition of description to STT0 in Figure 17-5 Format of IIC Control Register 0 (IICC0) (3/4)
p. 420
Addition of clearing condition to STCF and IICBSY in Figure 17-7 Format of IIC Flag Register 0 (IICF0)
p. 421
Modification of description in 17.3 (4) IIC clock selection register 0 (IICCL0)
pp. 422, 423
Modification of description in 17.3 (6) I
p. 423
Modification of Table 17-2 Selection Clock Setting
p. 428
Addition of cause that ACK is not returned to 17.5.4 Acknowledge (ACK)
p. 432
Addition of 17.5.7 Canceling wait
p. 437
Modification of Table 17-6 Wait Periods and Figure 17-20 Communication Reservation Timing
p. 440
Modification of Table 17-7 Wait Periods
pp. 440, 441
Addition of (4) to (6) to 17.5.15 Other cautions
pp. 442, 443
Modification of 17.5.16 (1) Master operation (single-master system) and (2) Master operation (multi-
master system)
pp. 447, 448
Modification of Figure 17-25 Slave Operation Flowchart (1) and Figure 17-26 Slave Operation
Flowchart (2)
p. 450
Addition of Note to (a) (i) When WTIM0 = 0 to and modification of (ii) When WTIM0 = 1 in 17.5.17 (1)
Master device operation
p. 451
Addition of Notes 1 to 3 to (b) (i) When WTIM0 = 0 in 17.5.17 (1) Master device operation
p. 452
Addition of Note to (c) (i) When WTIM0 = 0 in 17.5.17 (1) Master device operation
pp. 456, 460, 466,
Modification of the value of the following items of IICS0 register in 17.5.17
469
(2) (d) (i) When WTIM0 = 0 (after restart, does not match with address (= not extension code))
(2) (d) (ii) When WTIM0 = 1 (after restart, does not match with address (= not extension code))
(3) (d) (i) When WTIM0 = 0 (after restart, does not match with address (= not extension code))
(3) (d) (ii) When WTIM0 = 1 (after restart, does not match with address (= not extension code))
(6) (d) (ii) Extension code
(6) (e) When loss occurs due to stop condition during data transfer
(6) (h) (ii) When WTIM0 = 1
pp. 461, 463
Addition of description to 17.5.17 (5) Arbitration loss operation (operation as slave after arbitration loss)
and (6) Operation when arbitration loss occurs (no communication after arbitration loss)
640
APPENDIX D REVISION HISTORY
Description
2
C transfer clock setting method
Preliminary User's Manual U17260EJ3V1UD
(5/7)

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