Operation As Pwm Output - NEC 78K0 Series User Manual

9.4.2 Operation as PWM output

In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n
register during timer operation is prohibited.
The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n
register during timer operation is possible.
The operation in PWM output mode is as follows.
The TOHn output level is inverted and the 8-bit timer counter Hn is cleared to 0 when the 8-bit timer counter Hn
and the CMP0n register match after the timer count is started. The TOHn output level is inverted when the 8-bit timer
counter Hn and the CMP1n register match.
Setting
<1> Set each register.
(i) Setting timer H mode register n (TMHMDn)
TMHEn CKSn2
TMHMDn
0 0/1
(ii) Setting CMP0n register
• Compare value (N): Cycle setting
(iii) Setting CMP1n register
• Compare value (M): Duty setting
Remarks 1. n = 0, 1
2. 00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
<2> The count operation starts when TMHEn = 1.
<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled.
When the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is
cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output is inverted. At the same time,
the compare register to be compared with the 8-bit timer counter Hn is changed from the CMP0n register to
the CMP1n register.
<4> When the 8-bit timer counter Hn and the CMP1n register match, TOHn output is inverted and the compare
register to be compared with the 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n
register. At this time, the 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
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CHAPTER 9 8-BIT TIMERS H0 AND H1
Figure 9-11. Register Setting in PWM Output Mode
CKSn1 CKSn0 TMMDn1
0/1 0/1 1
Preliminary User's Manual U17260EJ3V1UD
TMMDn0 TOLEVn TOENn
0 0/1 1
Timer output enabled
Default setting of timer output level
PWM output mode selection
Count clock (f ) selection
CNT
Count operation stopped