NEC 78K0 Series User Manual page 199

CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-28. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Compare Register)
(a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 08H
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Count clear input
(TI00n pin input)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
TO0n pin output
(b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 0AH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Count clear input
(TI00n pin input)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
TO0n pin output
(a) and (b) differ as follows depending on the setting of bit 1 (TMC0n1) of the 16-bit timer mode control register 0n
(TMC0n).
(a) The output level of the TO0n pin is inverted when TM0n matches a compare register.
(b) The output level of the TO0n pin is inverted when TM0n matches a compare register or when the valid
edge of the TI00n pin is detected.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
M
N N
00 10
M
N
M
N N
00 10
M
N
Preliminary User's Manual U17260EJ3V1UD
M M
N
M M
N
M
N
M
N
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