NEC 78K0 Series User Manual page 214

FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
TO0n pin output
OVF0n bit
This is an application example where two compare registers are used in the free-running timer mode.
The output level of the TO0n pin is reversed each time the count value of TM0n matches the set value of CR00n
or CR01n. When the count value matches the register value, the INTTM00n or INTTM01n signal is generated.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
(2) Free-running timer mode operation
(CR00n: compare register, CR01n: capture register)
Count clock
Operable bits
TMC0n3, TMC0n2
Edge
TI00n pin
detection
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
214
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-38. Timing Example of Free-Running Timer Mode
(CR00n: Compare Register, CR01n: Compare Register)
• TOC0n = 13H, PRM0n = 00H, CRC0n = 00H, TMC0n = 04H
M
N
00 01
M
N
0 write clear
Figure 7-39. Block Diagram of Free-Running Timer Mode
(CR00n: Compare Register, CR01n: Capture Register)
Capture register
Capture signal
Preliminary User's Manual U17260EJ3V1UD
M M
N N
0 write clear
Timer counter
(TM0n)
Match signal
Compare register
(CR00n)
(CR01n)
M
N
0 write clear 0 write clear
Interrupt signal
(INTTM00n)
Output
TO0n pin
controller
Interrupt signal
(INTTM01n)
00