NEC 78K0 Series User Manual page 136

Clock operation mode
select register
(OSCCTL)
AMPH EXCLK OSCSEL
High-speed system
clock oscillator
f
XH
X1/P121 Crystal/ceramic
f
X
oscillation
X2/EXCLK/
External input
P122
f
EXCLK
clock
Subsystem
clock oscillator
XT1/P123
Crystal
f
XT
oscillation
f
SUB
XT2/EXCLKS/
P124 External input
f
EXCLKS
clock
XTSTART EXCLKS OSCSELS
Clock operation mode
Processor clock
control register select register
(OSCCTL)
(PCC)
Figure 6-1. Block Diagram of Clock Generator
Main OSC
Main clock
control register mode register
(MOC)
(MCM)
MSTOP MCS
stabilization time counter
STOP
MOST
Internal high-
f
RH
speed oscillator
(8 MHz (TYP.))
Internal bus
Oscillation stabilization
time select register (OSTS)
OSTS2 OSTS1 OSTS0 XSEL
3
X1 oscillation
Oscillation
stabilization
time counter
MOST MOST MOST MOST
11 13 14 15 16 status register
(OSTC)
Peripheral
hardware
clock switch
Controller
Main system
clock switch
Watch timer,
clock output
RSTS LSRSTOP RSTOP
Internal oscillation
mode register
(RCM)
Internal bus
Main clock Processor clock
mode register control register
(MCM) (PCC)
XTSTART CLS CSS PCC2 PCC1 PCC0
MCM0
4
To subsystem
clock oscillator
f
XP
Prescaler
f f f f
XP XP XP XP
2 3 4
2 2 2 2
f
SUB
2
1/2
Internal low-
f
RL
speed oscillator
(240 kHz (TYP.))
Option byte
1: Cannot be stopped
0: Can be stopped
Peripheral
hardware
clock (f )
PRS
CPU clock
(f )
CPU
Watchdog timer,
8-bit timer H1