NEC 78K0 Series User Manual page 201

CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Capture Register) (1/2)
(a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 08H, CR00n = 0001H
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n pin input)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
TO0n pin output
This is an application example where the output level of the TO0n pin is inverted when the count value has been
captured & cleared.
The count value is captured to CR01n and TM0n is cleared (to 0000H) when the valid edge of the TI00n pin is
detected. When the count value of TM0n is 0001H, a compare match interrupt signal (INTTM00n) is generated,
and the output level of the TO0n pin is inverted.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
M
00 10
0001H
0000H
Preliminary User's Manual U17260EJ3V1UD
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