NEC 78K0 Series User Manual page 207

CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register) (1/3)
(a) TOC0n = 13H, PRM0n = 30H, CRC0n = 05H, TMC0n = 0AH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n pin input)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
TO0n pin output
This is an application example where the count value is captured to CR01n, TM0n is cleared, and the TO0n pin
output is inverted when the rising or falling edge of the TI00n pin is detected.
When the edge of the TI01n pin is detected, an interrupt signal (INTTM00n) is generated. Mask the INTTM00n
signal when it is not used.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
L
M
00 10
0000H
L
0000H L
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