NEC 78K0 Series User Manual page 421

(4) IIC clock selection register 0 (IICCL0)
This register is used to set the transfer clock for the I
IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-
only. The SMC0, CL01, and CL00 bits are set in combination with bit 0 (CLX0) of IIC function expansion
register 0 (IICX0) (see 17.3 (6) I
Set IICCL0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation sets IICCL0 to 00H.
Figure 17-8. Format of IIC Clock Selection Register 0 (IICCL0)
Address: FFA8H After reset: 00H
Symbol 7
IICCL0 0
CLD0
0 The SCL0 pin was detected at low level.
1 The SCL0 pin was detected at high level.
Condition for clearing (CLD0 = 0)
• When the SCL0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
DAD0
0 The SDA0 pin was detected at low level.
1 The SDA0 pin was detected at high level.
Condition for clearing (DAD0 = 0)
• When the SDA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
SMC0
0 Operates in standard mode.
1 Operates in high-speed mode.
DFC0
0 Digital filter off.
1 Digital filter on.
Digital filter can be used only in high-speed mode.
In high-speed mode, the transfer clock does not vary regardless of DFC0 bit set (1)/clear (0).
The digital filter is used for noise elimination in high-speed mode.
Note Bits 4 and 5 are read-only.
Remark IICE0: Bit 7 of IIC control register 0 (IICC0)
CHAPTER 17 SERIAL INTERFACE IIC0
2
C transfer clock setting method).
Note
R/W
6 <5> <4>
0 CLD0 DAD0
Detection of SCL0 pin level (valid only when IICE0 = 1)
Detection of SDA0 pin level (valid only when IICE0 = 1)
Operation mode switching
Digital filter operation control
Preliminary User's Manual U17260EJ3V1UD
2
C bus.
<3> <2>
SMC0 DFC0 CL01
Condition for setting (CLD0 = 1)
• When the SCL0 pin is at high level
Condition for setting (DAD0 = 1)
• When the SDA0 pin is at high level
1 0
CL00
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