NEC 78K0 Series User Manual page 512

HALT Mode Setting
Item
System clock
Main system clock f
RH
f
X
f
EXCLK
Subsystem clock f
XT
f
EXCLKS
f
RL
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event 00
counter
Note
01
8-bit timer/event 50
counter
51
8-bit timer H0
H1
Watch timer
Watchdog timer
Clock output
Buzzer output
A/D converter
Serial interface UART0
UART6
CSI10
Note
CSI11
IIC0
Note
Multiplier/divider
Power-on-clear function
Low-voltage detection function
External interrupt
µ
Note PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only.
Remark f : Internal high-speed oscillation clock
RH
f : X1 clock
X
f : External main system clock
EXCLK
f : XT1 clock
XT
f : External subsystem clock
EXCLKS
f : Internal low-speed oscillation clock
RL
512
CHAPTER 21 STANDBY FUNCTION
Table 21-1. Operating Statuses in HALT Mode (1/2)
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (f )
RH
Clock supply to the CPU is stopped
Operation continues (cannot
be stopped)
Status before HALT mode
was set is retained
Operates or stops by external clock input
Status before HALT mode was set is retained
Operates or stops by external clock input
Status before HALT mode was set is retained
Operation stopped
Operation stopped
Status before HALT mode was set is retained
Status before HALT mode was set is retained
Operable
Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be
stopped by software" is set by option byte.
Operable
Preliminary User's Manual U17260EJ3V1UD
When CPU Is Operating on
X1 Clock (f )
X
Status before HALT mode was set is retained
Operation continues (cannot
be stopped)
When CPU Is Operating on
External Main System Clock
(f )
EXCLK
Status before HALT mode
was set is retained
Operation continues (cannot
be stopped)