Cpu Clock Status Transition Diagram - NEC 78K0 Series User Manual

6.6.6 CPU clock status transition diagram

Figure 6-14 shows the CPU clock status transition diagram of this product.
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Internal low-speed oscillation: Operable
(D)
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input: Operating
(G)
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operable
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operating
Remark In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the
above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (20
(TYP.)).
CHAPTER 6 CLOCK GENERATOR
Figure 6-14. CPU Clock Status Transition Diagram
(A)
Internal low-speed oscillation: Operable
(B)
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input:
Selectable by CPU
CPU: Operating
with XT1 oscillation or
EXCLKS input
CPU: XT1
oscillation/EXCLKS
input → HALT
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
Preliminary User's Manual U17260EJ3V1UD
Internal low-speed oscillation: Woken up
Power ON
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation/EXCLKS input: Stops (I/O port mode)
Reset release
Internal low-speed oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation/EXCLKS input: Stops (I/O port mode)
CPU: Operating
(H)
with internal high-
speed oscillation
CPU: Internal high-
speed oscillation
(E)
CPU: Internal high-
speed oscillation
(C)
CPU: Operating
with X1 oscillation or
EXCLK input
(I)
oscillation/EXCLK
(F)
input → STOP
CPU: X1
oscillation/EXCLK
input → HALT
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input: Operable
V < 1.59 V (TYP.)
DD
V 1.59 V (TYP.)
DD
V 1.8 V (MIN.)
DD
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
→ STOP
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Stops
Internal low-speed oscillation:
Operable
→ HALT
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operable
CPU: X1
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation: Stops
µ
s
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