Extension Code - NEC 78K0 Series User Manual

17.5.11 Extension code

(1) When the higher 4 bits of the receive address are either "0000" or "1111", the extension code reception flag
(EXC0) is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge
of the eighth clock. The local address stored in slave address register 0 (SVA0) is not affected.
(2) If "11110××0" is set to SVA0 by a 10-bit address transfer and "11110××0" is transferred from the master device,
the results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC0 = 1
• Seven bits of data match:
Remark EXC0: Bit 5 of IIC status register 0 (IICS0)
COI0: Bit 4 of IIC status register 0 (IICS0)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
code, such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, set bit 6 (LREL0) of the IIC control register 0 (IICC0) to 1 to set the standby mode for the next
communication operation.
Slave Address
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 0
1 1 1 1 0 X X
434
CHAPTER 17 SERIAL INTERFACE IIC0
COI0 = 1
Table 17-4. Extension Code Bit Definitions
R/W Bit
0 General call address
1 Start byte
×
C-BUS address
×
Address that is reserved for different bus format
×
10-bit slave address specification
Preliminary User's Manual U17260EJ3V1UD
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