Appendix D Revision History; Major Revisions In This Edition - NEC 78K0 Series User Manual

D.1 Major Revisions in This Edition
Page
CHAPTER 1 OUTLINE
Addition of Note on a product with on-chip debug function to and modification of operating ambient
pp. 17, 18
temperature in 1.1 Features
p. 18 Addition of special grade products supporting automotive equipment to 1.2 Applications
p. 19 Modification of 1.3 Ordering Information
p. 23, 24 Addition of 64-pin plastic TQFP (7x7), 64-pin plastic FLGA (5x5), Note to and modification of Caution 1 in 1.4
Pin Configuration (Top View)
pp. 27, 28 Modification of the following items on the function list in 1.5 78K0/Kx2 Series Lineup
• Supply voltage range of internal low-speed oscillation clock
• Detection voltage of POC
• Operating ambient temperature
p. 29 Addition of pin to "On-chip debug" in 1.6 Block Diagram
pp. 30, 31 Modification of the following items in 1.7 Outline of Functions
• Oscillation frequency range of high-speed system clock
• Supply voltage range of internal low-speed oscillation clock
• Operating ambient temperature
• Package
p. 31 Modification of outline of timer in 1.7 Outline of Functions
CHAPTER 2 PIN FUNCTIONS
p. 32 Modification of Table 2-1 Pin I/O Buffer Power Supplies
pp. 32 to 35 Addition of Note to 2.1 Pin Function List
p. 41 Modification of descriptions in 2.2.12 AV
p. 41 Addition of Caution to 2.2.15 REGC
p. 42 Modification of descriptions in 2.2.16 V
p. 44 Modification of recommended connection of unused pins of P121/X1, P122/X2/EXCLK, P123/XT1, and
P124/XT2/EXCLKS in Table 2-2 Pin I/O Circuit Types
CHAPTER 3 CPU ARCHITECTURE
p. 47 Addition of Caution 2 to 3.1 Memory Space
p. 47 Modification of Table 3-1 Set Values of Internal Memory Size Switching Register (IMS) and Internal
Expansion RAM Size Switching Register (IXS)
pp. 48 to 55 Modification of Figure 3-1 Memory Map (
p. 57 Modification of description in (3) Option byte area and (5) On-chip debug security ID setting area
µ
( PD78F0537D only) in 3.1.1
p. 58 Modification of description in 3.1.2 Memory bank (
pp. 65, 66 Addition of Note to Figure 3-14 Correspondence Between Data Memory and Addressing (
and Figure 3-15 Correspondence Between Data Memory and Addressing (
p. 77 Addition to description in 3.3 Instruction Address Addressing
p. 78 Addition to description in 3.3.2 Immediate addressing
p. 79 Addition to description in 3.3.3 Table indirect addressing
p. 82 Addition to description in 3.4.3 Direct addressing
p. 83 Modification of [Description example] in 3.4.4 Short direct addressing
636

APPENDIX D REVISION HISTORY

Description
REF
and EV
DD DD
µ
PD78F0531) to Figure 3-8 Memory Map (
Preliminary User's Manual U17260EJ3V1UD
, and 2.2.17 V and EV
SS SS
µ
PD78F0536, 78F0537, and 78F0537D only)
µ
PD78F0537, 78F0537D)
(1/7)
µ
PD78F0537D)
µ
PD78F0536)