NEC 78K0 Series User Manual page 159

(2) Example of setting procedure when using the external subsystem clock
<1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and
OSCCTL registers)
When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from
port mode to external clock input mode. In this case, input the external clock to the EXCLKS/XT2/P124
pins.
XTSTART EXCLKS
0
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
operating.
(3) Example of setting procedure when using the subsystem clock as the CPU clock
<1> Setting subsystem clock oscillation
(See 6.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of
setting procedure when using the external subsystem clock.)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
<2> Switching the CPU clock (PCC register)
When CSS is set to 1, the subsystem clock is supplied to the CPU.
CSS PCC2
1
(4) Example of setting procedure when stopping the subsystem clock
<1> Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal
high-speed oscillation clock or high-speed system clock.
CLS MCS
0
0
1
<2> Stopping the subsystem clock (OSCCTL register)
When OSCSELS is cleared to 0, XT1 oscillation is stopped (the input of the external clock is disabled).
Caution1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch
timer if it is operating on the subsystem clock.
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
CHAPTER 6 CLOCK GENERATOR
OSCSELS Operation Mode of
Subsystem Clock Pin
1 1 External clock input
mode
Note
PCC1 PCC0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
Other than above
0 Internal high-speed oscillation clock
1 High-speed system clock
×
Subsystem clock
Preliminary User's Manual U17260EJ3V1UD
P123/XT1 Pin
I/O port
CPU Clock (f ) Selection
CPU
f /2
SUB
Setting prohibited
CPU Clock Status
P124/XT2/
EXCLKS Pin
External clock input
159