NEC 78K0 Series User Manual page 132

Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2)
Pin Name
Note 1
P20 to P27 ANI0 to ANI7
P30 to P32 INTP1 to INTP3
P33 INTP4
TI51
TO51
P60 SCL0
P61 SDA0
P62 EXSCL0
P70 to P77 KR0 to KR7
P120 INTP0
EXLVI
Note 2
P121 X1
Note 2
P122 X2
Note 2
EXCLK
Note 2
P123 XT1
Note 2
P124 XT2
Note 2
EXCLKS
P140 PCL
INTP6
P141 BUZ
INTP7
Remarks 1. ×:
Don't care
PM××: Port mode register
P××: Port output latch
2. The X1, X2, P31, and P32 pins of the
pins (OCD0A, OCD0B, OCD1A, OCD1B) when the on-chip debug function is used. For details, see
CHAPTER 27 ON-CHIP DEBUG FUNCTION (
(Notes 1 and 2 are listed on the next page.)
132
CHAPTER 5 PORT FUNCTIONS
Alternate Function
Function Name
Note 1
Preliminary User's Manual U17260EJ3V1UD
I/O
Input
Input
Input
Input
Output
I/O
I/O
Input
Input
Input
Input
−
−
Input
−
−
Input
Output
Input
Output
Input
µ
PD78F0537D can be used as on-chip debug mode setting
µ
PD78F0537D ONLY).
PM×× P××
×
1
×
1
×
1
×
1
0 0
0 0
0 0
×
1
×
1
×
1
×
1
× ×
× ×
× ×
× ×
× ×
× ×
0 0
×
1
0 0
×
1