NEC 78K0 Series User Manual page 405

(5) SO1n output (see (a) in Figures 16-1 and 16-2)
The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is
cleared to 0.
TRMD1n
Note 2
TRMD1n = 0
TRMD1n = 1
Notes 1. The actual output of the SO10/P12 or SO11/P02 pin is determined according to PM12 and P12
or PM02 and P02, as well as the SO1n output.
2. Status after reset
Caution If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes.
Remark n = 0:
n = 0, 1:
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
Table 16-3. SO1n Output Status
DAP1n
−
DAP1n = 0
DAP1n = 1 DIR1n = 0
DIR1n = 1
µ
PD78F0531, 78F0532, 78F0533
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Preliminary User's Manual U17260EJ3V1UD
DIR1n SO1n Output
−
Outputs low level
−
Value of SO1n latch
(low-level output)
Value of bit 7 of SOTB1n
Value of bit 0 of SOTB1n
Note 1
Note 2
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