NEC 78K0 Series User Manual page 177

Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address: FFBAH After reset: 00H
Symbol 7
TMC00 0
TMC003
0
0
1
1
TMC001
• Match between TM00 and CR000 or match between TM00 and CR010
0
• Match between TM00 and CR000 or match between TM00 and CR010
1
• Trigger input of TI000 pin valid edge
OVF00
Clear (0) Clears OVF00 to 0 or TMC003 and TMC002 = 00
Set (1) Overflow occurs.
OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running
timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match
between TM00 and CR000).
It can also be set to 1 by writing 1 to OVF00.
Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00).
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
R/W
6 5
0 0
TMC002
0 Disables TM00 operation. Stops supplying operating clock. Asynchronously resets
the internal circuit.
1 Free-running timer mode
0 Clear & start mode entered by TI000 pin valid edge input
1 Clear & start mode entered upon a match between TM00 and CR000
Condition to reverse timer output (TO00)
Preliminary User's Manual U17260EJ3V1UD
4 3
0 TMC003 TMC002
Operation enable of 16-bit timer/event counter 00
TM00 overflow flag
2 1 <0>
TMC001 OVF00
Note
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