Page 1 User’s Manual 78K0S/KU1+ 8-Bit Single-Chip Microcontrollers µ PD78F9200 µ PD78F9201 µ PD78F9202 Document No. U18172EJ2V0UD00 (2nd edition) Date Published January 2008 NS © 2006 Printed in Japan...
Page 2 [MEMO] User’s Manual U18172EJ2V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the 78K0S/KU1+ in order to design and develop its application systems and programs. The target devices are the following subseries products. • 78K0S/KU1+: µ...
Page 6 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: ××× (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ...
Page 7 Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 8: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW.........................14 1.1 Features ............................14 1.2 Ordering Information........................15 1.3 Pin Configuration (Top View) ......................16 1.4 78K0S/Kx1+ Product Lineup......................17 1.5 Block Diagram..........................18 1.6 Functional Outline ........................19 CHAPTER 2 PIN FUNCTIONS .......................20 2.1 Pin Function List...........................20 2.2 Pin Functions ..........................22 2.2.1 P20 to P23 (Port 2)..........................22 2.2.2 P32 and P34 (Port 3).........................23 2.2.3 P40 and P43 (Port 4).........................23...
Page 9 3.4.6 Based addressing ..........................49 3.4.7 Stack addressing..........................50 CHAPTER 4 PORT FUNCTIONS......................51 4.1 Functions of Ports........................51 4.2 Port Configuration........................52 4.2.1 Port 2 ..............................52 4.2.2 Port 3 ..............................56 4.2.3 Port 4 ..............................57 4.3 Registers Controlling Port Functions ..................58 4.4 Operation of Port Function......................
Page 10 7.2 Configuration of 8-Bit Timer H1 ....................122 7.3 Registers Controlling 8-Bit Timer H1..................125 7.4 Operation of 8-Bit Timer H1 .......................127 7.4.1 Operation as interval timer/square-wave output ................127 7.4.2 Operation as PWM output mode .....................131 CHAPTER 8 WATCHDOG TIMER .......................137 8.1 Functions of Watchdog Timer ....................137 8.2 Configuration of Watchdog Timer ....................139 8.3 Registers Controlling Watchdog Timer..................140 8.4 Operation of Watchdog Timer ....................142...
Page 11 11.2 Standby Function Operation ....................180 11.2.1 HALT mode ........................... 180 11.2.2 STOP mode ..........................183 CHAPTER 12 RESET FUNCTION .......................187 12.1 Register for Confirming Reset Source...................194 CHAPTER 13 POWER-ON-CLEAR CIRCUIT ..................195 13.1 Functions of Power-on-Clear Circuit..................195 13.2 Configuration of Power-on-Clear Circuit ................196 13.3 Operation of Power-on-Clear Circuit..................
Page 12 16.8.4 Example of shifting normal mode to self programming mode ............232 16.8.5 Example of shifting self programming mode to normal mode ............235 16.8.6 Example of block erase operation in self programming mode ............238 16.8.7 Example of block blank check operation in self programming mode ..........241 16.8.8 Example of byte write operation in self programming mode ............244 16.8.9 Example of internal verify operation in self programming mode ............247 16.8.10 Examples of operation when command execution time should be minimized in self programming...
Page 13 APPENDIX C REGISTER INDEX......................304 C.1 Register Index (Register Name) ....................304 C.2 Register Index (Symbol)......................306 APPENDIX D LIST OF CAUTIONS.....................308 APPENDIX E REVISION HISTORY .....................323 E.1 Major Revisions in This Edition....................323 User’s Manual U18172EJ2V0UD...
Page 14: Chapter 1 Overview
CHAPTER 1 OVERVIEW 1.1 Features <R> O 78K0S CPU core O ROM and RAM capacities Item Program Memory (Flash Memory) Memory (Internal High-Speed RAM) Part number µ PD78F9200 1 KB 128 bytes µ PD78F9201 2 KB µ PD78F9202 4 KB µ...
Page 15: Ordering Information
CHAPTER 1 OVERVIEW O Supply voltage: V = 2.0 to 5.5 V ∗ Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (V ) of the power-on clear (POC) circuit is 2.1 V ±0.1 V. = −40 to +85°C O Operating temperature range: T 1.2 Ordering Information...
Page 16: Pin Configuration (Top View)
CHAPTER 1 OVERVIEW 1.3 Pin Configuration (Top View) 10-pin plastic SSOP P20/ANI0/TI000/TOH1 P21/ANI1/TI010/TO00/INTP0 Note1 P32/INTP1 Note2 P34/RESET P23/X1/ANI3 P22/X2/ANI2 ANI0 to ANI3: Analog input TI000, TI010: Timer input INTP0, INTP1: External interrupt input TO00, TOH1: Timer output Note2 P20 to P23: Port 2 Power supply Note1...
Page 17: 78K0S/Kx1+ Product Lineup
CHAPTER 1 OVERVIEW 1.4 78K0S/Kx1+ Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number 78K0S/KU1+ 78K0S/KY1+ 78K0S/KA1+ 78K0S/KB1+ Item Number of pins 10 pins 16 pins 20 pins 30/32 pins Internal Flash memory 1 KB, 2 KB, 4 KB 2 KB 4 KB 4 KB, 8 KB...
Page 18: Block Diagram
CHAPTER 1 OVERVIEW 1.5 Block Diagram TO00/TI010/P21 PORT 2 P20-P23 16-bit TIMER/ EVENT COUNTER 00 TI000/P20 PORT 3 TOH1/P20 78K0S 8-bit TIMER H1 FLASH MEMORY CORE PORT 4 P40, P43 LOW-SPEED INTERNAL OSCILLATOR POWER ON CLEAR/ POC/LVI LOW VOLTAGE CONTROL INDICATOR WATCHDOG TIMER INTERNAL...
Page 19: Functional Outline
CHAPTER 1 OVERVIEW 1.6 Functional Outline µ µ µ Item PD78F9200 PD78F9201 PD78F9202 Internal Flash memory 1 KB 2 KB 4 KB memory High-speed RAM 128 bytes Memory space 64 KB X1 input clock (oscillation frequency) Crystal/ceramic/external clock input: 10 MHz (V = 2.0 to 5.5 V) Internal High speed (oscillation...
Page 20: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List (1) Port pins Pin Name Function After Reset Alternate-Function Port 2. Input ANI0/TI000/TOH1 4-bit I/O port. ANI1/TI010/ Can be set to input or output mode in 1-bit units. TO00/INTP0 An on-chip pull-up resistor can be connected by setting Note 1 Note 1 X2/ANI2...
Page 21 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name Function After Reset Alternate- Function Pin INTP0 Input External interrupt input for which the valid edge (rising edge, Input P21/ANI1/TI010/ falling edge, or both rising and falling edges) can be specified TO00 INTP1 TI000...
Page 22: Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Functions 2.2.1 P20 to P23 (Port 2) P20 to P23 constitute a 4-bit I/O port. In addition to the function as I/O port pins, these pins also have a function to input an analog signal to the A/D converter, input/output a timer signal, and input an external interrupt request signal. P22 and P23 also function as the X2/ANI2 and X1/ANI3, respectively.
Page 23: P32 And P34 (Port 3)
CHAPTER 2 PIN FUNCTIONS 2.2.2 P32 and P34 (Port 3) P32 is a 1-bit I/O port. In addition to the function as an I/O port pin, this pin also has a function to input an external interrupt request signal. P34 is a 1-bit input-only port. This pin is also used as a RESET pin, and when the power is turned on, this is the reset function.
Page 24: Pin I/O Circuits And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Connection of Unused Pins Table 2-1 shows I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 2-1. Table 2-1.
Page 25 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 2 Type 36 feedback cut-off P-ch Schmitt-triggered input with hysteresis characteristics enable IN/OUT IN/OUT Type 8-A pullup P-ch enable Pull up P-ch enable data P-ch output N-ch disable Data P-ch Comparator P-ch IN/OUT...
Page 26: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The 78K0S/KU1+ can access up to 64 KB of memory space. Figures 3-1 to 3-3 show the memory maps. µ Figure 3-1. Memory Map ( PD78F9200) F F F F H Special function registers (SFR) 256 ×...
Page 27 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-2. Memory Map ( PD78F9201) F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM 128 × 8 bits F E 8 0 H F E 7 F H Use prohibited...
Page 28 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-3. Memory Map ( PD78F9202) F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM 128 × 8 bits F E 8 0 H F D 7 F H Use prohibited...
Page 29: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The 78K0S/KU1+ provide the following internal ROMs (or flash memory) containing the following capacities. Table 3-1.
Page 30: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space 128-byte internal high-speed RAM is provided in the 78K0S/KU1+. The internal high-speed RAM can also be used as a stack memory. 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3).
Page 31 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-5. Data Memory Addressing ( PD78F9201) F F F F H Special function registers (SFR) SFR addressing 256 × 8 bits F F 2 0 H F E 1 F H F F 0 0 H F E F F H Short direct addressing Internal high-speed RAM...
Page 32 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-6. Data Memory Addressing ( PD78F9202) F F F F H Special function registers (SFR) SFR addressing 256 × 8 bits F F 2 0 H F E 1 F H F F 0 0 H F E F F H Short direct addressing Internal high-speed RAM...
Page 33: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0S/KU1+ provide the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 34 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled. When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources.
Page 35 CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area (Other than the internal high-speed RAM area cannot be set as the stack area).
Page 36: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 37: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions.
Page 38 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (1/3) Address Symbol Bit No. Number of Bits After Manipulated Reset Simultaneously − − − − − − − − − − − − − − − FF00H, FF01H √ √ −...
Page 39 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (2/3) Address Symbol Bit No. Number of Bits After Manipulated Reset Simultaneously − − − − − − − − − − − − − − − FF52H, FF53H − √ −...
Page 40 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (3/3) Address Symbol Bit No. Number of Bits After Manipulated Reset Simultaneously √ √ − FFA6H FLAPHC FLAP FLAP FLAP FLAP √ √ − FFA7H FLAPLC FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP...
Page 41: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 42: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CALL or BR...
Page 43: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration] User’s Manual U18172EJ2V0UD...
Page 44: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...
Page 45: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 160-byte space FE80H to FF1FH (FE80H to FEFFH (internal high-speed RAM) + FF00H to FF1FH (special function registers)).
Page 46: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH are accessed with short direct addressing.
Page 47: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 48: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.
Page 49: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored.
Page 50: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt request generation. Stack addressing can be used to access the internal high-speed RAM area only.
Page 51: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS Functions of Ports The 78K0S/KU1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1 shows the functions of each port. In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to CHAPTER 2 PIN FUNCTIONS.
Page 52: Port Configuration
CHAPTER 4 PORT FUNCTIONS Port Configuration Ports consist of the following hardware units. Table 4-2. Configuration of Ports Item Configuration Control registers Port mode registers (PM2 to PM4) Port registers (P2 to P4) Port mode control register 2 (PMC2) Pull-up resistor option registers (PU2 to PU4) Ports Total: 8 (CMOS I/O: 7, CMOS input: 1) Pull-up resistor...
Page 53 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P20 and P21 PU20, PU21 P-ch PMC2 PMC20, PMC21 Alternate function PORT Output latch P20/ANI0/TI000/TOH1, (P20, P21) P21/ANI1/TI010/TO00/INTP0 PM20, PM21 Alternate function A/D converter Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port mode control register 2...
Page 54 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P22 PU22 P-ch PMC2 PMC22 PORT Output latch P22/ANI2/X2 (P22) PM22 A/D converter Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 Read signal WR××: Write signal User’s Manual U18172EJ2V0UD...
Page 55 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P23 PU23 P-ch PMC2 PMC23 PORT Output latch P23/ANI3/X1 (P23) PM23 A/D converter Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 Read signal WR××: Write signal User’s Manual U18172EJ2V0UD...
Page 56: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 3 The P32 pin is a 1-bit I/O port with an output latch. This pin can be set to the input or output mode by using port mode register 3 (PM3). When this pin is used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3).
Page 57: Port 4
CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P34 P34/RESET Reset Option byte Read signal Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte.
Page 58: Registers Controlling Port Functions
CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P40 and P43 PU40, PU43 P-ch PORT Output latch P40, P43 (P40, P43) PM40, PM43 Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal Registers Controlling Port Functions The ports are controlled by the following four types of registers.
Page 59 CHAPTER 4 PORT FUNCTIONS (1) Port mode registers (PM2 to PM4) These registers are used to set the corresponding port to the input or output mode in 1-bit units. Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.
Page 60 CHAPTER 4 PORT FUNCTIONS (2) Port registers (P2 to P4) These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip. When a port register is read, the pin level is read in the input mode, and the value of the output latch of the port is read in the output mode.
Page 61 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Format of Port Mode Control Register 2 Address: FF84H, After reset: R/W Symbol PMC2 PMC23 PMC22 PMC21 PMC20 PMC2n Specification of operation mode (n = 0 to 3) Port/alternate-function (except the A/D converter function) mode User’s Manual U18172EJ2V0UD...
Page 62 CHAPTER 4 PORT FUNCTIONS (4) Pull-up resistor option registers (PU2 to PU4) These registers are used to specify whether an on-chip pull-up resistor is connected to P20 to P23, P32, P40 and P43. By setting PU2 to PU4, an on-chip pull-up resistor can be connected to the port pin corresponding to the bit of PU2 to PU4.
Page 63: Operation Of Port Function
CHAPTER 4 PORT FUNCTIONS Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units.
Page 64: Chapter 5 Clock Generators
CHAPTER 5 CLOCK GENERATORS Functions of Clock Generators The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the watchdog timer and 8-bit timer H1 (TMH1).
Page 65: Configuration Of Clock Generators
CHAPTER 5 CLOCK GENERATORS Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1. Configuration of Clock Generators Item Configuration Control registers Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) Oscillation stabilization time select register (OSTS) Oscillators Crystal/ceramic oscillator...
Page 66 CHAPTER 5 CLOCK GENERATORS Figure 5-1. Block Diagram of Clock Generators Internal bus Oscillation stabilization Preprocessor clock Processor clock time select register (OSTS) control register (PPCC) control register (PCC) OSTS1 OSTS0 PPCC1 PPCC0 PCC1 System clock oscillation Controller stabilization time counter CPU clock STOP Watchdog timer...
Page 67: Registers Controlling Clock Generators
CHAPTER 5 CLOCK GENERATORS Registers Controlling Clock Generators The clock generators are controlled by the following four registers. • Processor clock control register (PCC) • Preprocessor clock control register (PPCC) • Low-speed internal oscillation mode register (LSRCM) • Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) and preprocessor clock control register (PPCC) These registers are used to specify the division ratio of the system clock.
Page 68 CHAPTER 5 CLOCK GENERATORS The fastest instruction of the 78K0S/KU1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (f ) and the minimum instruction execution time is as shown in Table 5-2. Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time Note CPU Clock (f Minimum Instruction Execution Time: 2/f...
Page 69 CHAPTER 5 CLOCK GENERATORS (3) Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the STOP mode is released.
Page 70: System Clock Oscillators
CHAPTER 5 CLOCK GENERATORS System Clock Oscillators The following three types of system clock oscillators are available. • High-speed internal oscillator: Internally oscillates a clock of 8 MHz (TYP.). • Crystal/ceramic oscillator: Oscillates a clock of 2 MHz to 10 MHz. •...
Page 71 CHAPTER 5 CLOCK GENERATORS Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (b) Crossed signal lines PORT (d) Current flowing through ground line of oscillator (c) Wiring near high fluctuating current (Potential at points A, B, and C fluctuates.) PORT...
Page 72: External Clock Input Circuit
CHAPTER 5 CLOCK GENERATORS Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched 5.4.3 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin. If external clock input is selected by the option byte as the system clock source, the X2 pin can be used as an I/O port pin.
Page 73: Operation Of Cpu Clock Generator
CHAPTER 5 CLOCK GENERATORS Operation of CPU Clock Generator A clock (f ) is supplied to the CPU from the system clock (f ) oscillated by one of the following three types of oscillators. • High-speed internal oscillator: Internally oscillates a clock of 8 MHz (TYP.). •...
Page 74 CHAPTER 5 CLOCK GENERATORS (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then the high-speed internal oscillation clock operates as the system clock.
Page 75 CHAPTER 5 CLOCK GENERATORS (2) Crystal/ceramic oscillator If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 MHz to 10 MHz can be selected and the accuracy of processing is improved because the frequency deviation is small, as compared with high- speed internal oscillation (8 MHz (TYP.)).
Page 76 CHAPTER 5 CLOCK GENERATORS Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation Power application > 2.1 V ±0.1 V Reset by power-on clear Reset signal Crystal/ceramic oscillation selected by option byte Wait for clock oscillation stabilization Start with PCC = 02H, PPCC = 02H Clock division ratio variable during...
Page 77 CHAPTER 5 CLOCK GENERATORS (3) External clock input circuit If external clock input is selected by the option byte, the following is possible. • High-speed operation The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.)) because an oscillation frequency of 2 MHz to 10 MHz can be selected and an external clock with a small frequency deviation can be supplied.
Page 78 CHAPTER 5 CLOCK GENERATORS Figure 5-13. Status Transition of Default Start by External Clock Input Power application > 2.1 V ±0.1 V Reset by power-on clear Reset signal External clock input selected by option byte Start with PCC = 02H, PPCC = 02H Clock division ratio variable during...
Page 79: Operation Of Clock Generator Supplying Clock To Peripheral Hardware
CHAPTER 5 CLOCK GENERATORS Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. • Clock to peripheral hardware (f • Low-speed internal oscillation clock (f (1) Clock to peripheral hardware The clock to the peripheral hardware is supplied by dividing the system clock (f ).
Page 80 CHAPTER 5 CLOCK GENERATORS Figure 5-14. Status Transition of Low-Speed Internal Oscillator Power application > 2.1 V ±0.1 V Reset by power-on clear Reset signal Select by option byte if low-speed internal oscillator can be stopped or not Can be stopped Cannot be stopped Clock source of Clock source of...
Page 81: Chapter 6 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates interrupt requests at the preset time interval. • Number of counts: 2 to 65536 (2) External event counter 16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of valid level pulse width or more of a signal input externally.
Page 82: Configuration Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Timer counter 16-bit timer counter 00 (TM00) Register 16-bit timer capture/compare registers 000, 010 (CR000, CR010) Timer input TI000, TI010 Timer output...
Page 83 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read.
Page 84 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 • When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 6- Table 6-2.
Page 85 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer capture/compare register 010 (CR010) CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00).
Page 86: Registers To Control 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 6. Changing the CR010 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. Registers to Control 16-Bit Timer/Event Counter 00 The following seven types of registers are used to control 16-bit timer/event counter 00.
Page 87 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FF60H After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear TO00 inversion timing selection Interrupt request generation mode selection Operation stop...
Page 88 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Remark TM00: 16-bit timer counter 00 CR000: 16-bit timer capture/compare register 000 CR010: 16-bit timer capture/compare register 010 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit capture/compare registers (CR000, CR010). CRC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 89 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot pulse output operation enable/disable, and output trigger of one-shot pulse by software.
Page 90 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Caution 6. When the TOE00 is 0, set the TOE00, LVS00, and LVR00 at the same time with the 8-bit memory manipulation instruction. When the TOE00 is 1, the LVS00 and LVR00 can be set with the 1-bit memory manipulation instruction.
Page 91 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. <1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled →...
Page 92: Operation Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Format of Port Mode Control Register 2 (PMC2) Address: FF84H After reset: 00H R/W Symbol PMC2 PMC23 PMC22 PMC21 PMC20 PMC2n Specification of operation mode (n = 0 to 3) Port/Alternate-function (except A/D converter) mode A/D converter mode Operation of 16-Bit Timer/Event Counter 00 6.4.1...
Page 93 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-11. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00 CR000 used as compare register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001...
Page 94: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-13. Timing of Interval Timer Operation Count clock TM00 count value 0000H 0001H 0000H 0001H 0000H 0001H Timer operation enabled Clear Clear CR000 INTTM000 Interrupt request generated Interrupt request generated Remark Interval time = (N + 1) × t N = 0001H to FFFFH (settable range) When the compare register is changed during timer count operation, if the value after 16-bit timer capture/compare register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting,...
Page 95 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is cleared to 0 and the interrupt request signal (INTTM000) is generated.
Page 96 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-16. External Event Counter Configuration Diagram Internal bus 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear Note Noise eliminator 16-bit timer counter 00 (TM00) OVF00 Valid edge of TI000 Note OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH. Figure 6-17.
Page 97: Pulse Width Measurement Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
Page 98 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-19. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI000 and CR010 Are Used) (a) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00 CR000 used as compare register CR010 used as capture register (b) Prescaler mode register 00 (PRM00) ES101...
Page 99 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H TM00 count value TI000 pin input CR010 capture value INTTM010...
Page 100 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-22. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00 CR000 used as capture register Captures valid edge of TI010 pin to CR000. CR010 used as capture register (b) Prescaler mode register 00 (PRM00) ES110...
Page 101 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) User’s Manual U18172EJ2V0UD...
Page 102 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00 CR000 used as capture register Captures to CR000 at inverse edge Note to valid edge of TI000...
Page 103 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-25. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM00 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI000 pin input CR010 capture value...
Page 104 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-26. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (2/2) (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000 PRM00 Selects count clock (setting “11” is prohibited). Specifies rising edge for pulse width detection.
Page 105: Square-Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-28 for the set value). <3>...
Page 106 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-28. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 TOC00 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting “11”...
Page 107: Ppg Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and User’s Manual U18172EJ2V0UD...
Page 108 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Control Register Settings for PPG Output Operation (a) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 × CRC00 CR000 used as compare register CR010 used as compare register (b) 16-bit timer output control register 00 (TOC00) OSPT00 OSPE00 TOC004...
Page 109 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Configuration Diagram of PPG Output 16-bit timer capture/compare register 000 (CR000) Clear 16-bit timer counter 00 circuit (TM00) Noise TI000/ANI0/ eliminator TOH1/P20 TO00/TI010/ANI1/ INTP0/P21 16-bit timer capture/compare register 010 (CR010) Figure 6-32. PPG Output Operation Timing Count clock M −...
Page 110: One-Shot Pulse Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1>...
Page 111 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM010 PRM00 Selects count clock. Setting invalid (setting “10” is prohibited.) Setting invalid (setting “10”...
Page 112 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 04H (TM00 count starts) Count clock − − TM00 count 0000H 0001H N + 1 0000H M + 1 M + 2 CR010 set value CR000 set value OSPT00...
Page 113 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-35. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000 PRM00 Selects count clock (setting “11” is prohibited). Specifies the rising edge for pulse width detection.
Page 114 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-36. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) Count clock − − TM00 count value 0000H 0001H 0000H N + 1 N + 2 M + 1 M + 2 CR010 set value...
Page 115: Cautions Related To 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions Related to 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
Page 116 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Capture register data retention The values of 16-bit timer capture/compare registers 0n0 (CR0n0) after 16-bit timer/event counter 00 has stopped are not guaranteed. Remark n = 0, 1 (5) Setting of 16-bit timer mode control register 00 (TMC00) The timer operation must be stopped before writing to bits other than the OVF00 flag.
Page 117 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 <3> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H. (12) One-shot pulse output with external trigger <1> Do not input the external trigger again while the one-shot pulse is output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed.
Page 118 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-39. Capture Register Data Retention Timing Count clock TM00 count value N + 1 N + 2 M + 1 M + 2 Edge input INTTM010 Capture read signal CR010 capture value N + 2 M + 1 Capture Capture, but...
Page 119 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (17) Changing compare register during timer operation <1> With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare register, when changing CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the timing of the match, so the operation is not guaranteed in such cases.
Page 120 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (18) Edge detection <1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. (a) Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled →...
Page 121 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (23) External clock limitation <1> When using an input pulse of the TI000 pin as a count clock (external trigger), be sure to input the pulse width which satisfies the AC characteristics. For the AC characteristics, refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS.
Page 122: Chapter 7 8-Bit Timer H1
CHAPTER 7 8-BIT TIMER H1 Functions of 8-Bit Timer H1 8-bit timer H1 has the following functions. • Interval timer • PWM output mode • Square-wave output Configuration of 8-Bit Timer H1 8-bit timer H1 consists of the following hardware. Table 7-1.
Page 123 Figure 7-1. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode register 1 (TMHMD1) 8-bit timer H 8-bit timer H TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 compare register compare register 11 (CMP11) 01 (CMP01) Decoder TOH1/TI000/ ANI1/P20 Selector...
Page 124 CHAPTER 7 8-BIT TIMER H1 (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-2. Format of 8-Bit Timer H Compare Register 01 (CMP01) Address: FF0EH After reset: 00H Symbol...
Page 125: Registers Controlling 8-Bit Timer H1
CHAPTER 7 8-BIT TIMER H1 Registers Controlling 8-Bit Timer H1 The following four registers are used to control 8-Bit Timer H1. • 8-bit timer H mode register 1 (TMHMD1) • Port mode register 2 (PM2) • Port register 2 (P2) •...
Page 126 CHAPTER 7 8-BIT TIMER H1 Figure 7-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF70H After reset: 00H <7> <1> <0> Symbol TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stop timer count operation (counter is cleared to 0) Enable timer count operation (count operation started by inputting clock) CKS12 CKS11...
Page 127: Operation Of 8-Bit Timer H1
CHAPTER 7 8-BIT TIMER H1 (2) Port mode register 2 (PM2) and port mode control register 2 (PMC2) When using the P20/TOH1/TI000/ANI0 pin for timer output, clear PM20, the output latch of P20, and PMC20 to 0. PM2 and PMC2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM2 to FFH, and clears PMC2 to 00H.
Page 128 CHAPTER 7 8-BIT TIMER H1 (1) Usage Generates the INTTMH1 signal repeatedly at the same interval. <1> Set each register. Figure 7-7. Register Setting During Interval Timer/Square-Wave Output Operation Setting timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1...
Page 129 CHAPTER 7 8-BIT TIMER H1 Figure 7-8. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (01H ≤ CMP01 ≤ FEH) Count clock Count start 01H 00H 8-bit timer counter H1 Clear Clear CMP01 TMHE1 INTTMH1 Interval time TOH1 <1>...
Page 130 CHAPTER 7 8-BIT TIMER H1 Figure 7-8. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP01 = FFH Count clock Count start 8-bit timer counter H1 Clear Clear CMP01 TMHE1 INTTMH1 TOH1 Interval time (c) Operation when CMP01 = 00H Count clock Count start 8-bit timer counter H1...
Page 131: Operation As Pwm Output Mode
CHAPTER 7 8-BIT TIMER H1 7.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited.
Page 132 CHAPTER 7 8-BIT TIMER H1 <4> When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register.
Page 133 CHAPTER 7 8-BIT TIMER H1 Figure 7-10. Operation Timing in PWM Output Mode (1/4) (a) Basic operation (00H < CMP11 < CMP01 < FFH) Count clock 8-bit timer counter H1 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H CMP01 CMP11...
Page 134 CHAPTER 7 8-BIT TIMER H1 Figure 7-10. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP01 CMP11 TMHE1...
Page 135 CHAPTER 7 8-BIT TIMER H1 Figure 7-10. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter H1 CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0)
Page 136 CHAPTER 7 8-BIT TIMER H1 Figure 7-10. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 = A5H) Count clock 8-bit timer counter H1 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP01...
Page 137: Chapter 8 Watchdog Timer
CHAPTER 8 WATCHDOG TIMER Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 12 RESET FUNCTION.
Page 138 CHAPTER 8 WATCHDOG TIMER Table 8-2. Option Byte Setting and Watchdog Timer Operation Mode Option Byte Setting User’s Manual U18172EJ2V0UD...
Page 139: Configuration Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 8-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 8-1. Block Diagram of Watchdog Timer Clock Output 16-bit...
Page 140: Registers Controlling Watchdog Timer
CHAPTER 8 WATCHDOG TIMER Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer mode register (WDTM) • Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released.
Page 141 CHAPTER 8 WATCHDOG TIMER Cautions 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. However, at the first write, if “1” and “x” are set for WDCS4 and WDCS3 respectively and the watchdog timer is stopped, then the internal reset signal does not occur even if the following are executed.
Page 142: Operation Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER Operation of Watchdog Timer 8.4.1 Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to low-speed internal oscillation clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 143 CHAPTER 8 WATCHDOG TIMER Figure 8-4. Status Transition Diagram When “Low-Speed Internal Oscillator Cannot Be Stopped” Is Selected by Option Byte Reset WDT clock: f Overflow time: 546.13 ms (MAX.) WDTE = “ACH” Clear WDT counter. WDT clock is fixed to f Select overflow time (settable only once).
Page 144: Watchdog Timer Operation When "Low-Speed Internal Oscillator Can Be Stopped By Software" Is Selected By Option Byte
CHAPTER 8 WATCHDOG TIMER 8.4.2 Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or system clock.
Page 145 CHAPTER 8 WATCHDOG TIMER Figure 8-5. Status Transition Diagram When “Low-Speed Internal Oscillator Can Be Stopped by Software” Is Selected by Option Byte Reset WDT clock: f Overflow time: 546.13 ms (MAX.) WDCS4 = 1 WDT clock = f Select overflow time (settable only once).
Page 146: Watchdog Timer Operation In Stop Mode (When "Low-Speed Internal Oscillator Can Be Stopped By Software" Is Selected By Option Byte)
CHAPTER 8 WATCHDOG TIMER 8.4.3 Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or low-speed internal oscillation clock is being used.
Page 147: Watchdog Timer Operation In Halt Mode (When "Low-Speed Internal Oscillator Can Be Stopped By Software" Is Selected By Option Byte)
CHAPTER 8 WATCHDOG TIMER (2) When the watchdog timer operation clock is the low-speed internal oscillation clock (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is µ...
Page 148: Chapter 9 A/D Converter
CHAPTER 9 A/D CONVERTER Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following function. •...
Page 149 CHAPTER 9 A/D CONVERTER Table 9-1. Sampling Time and A/D Conversion Time Reference Sampling Conversion = 8 MHz = 10 MHz Note 2 Note 3 Voltage Time Time Sampling Conversion Sampling Conversion Note 1 Range Note 2 Note 3 Note 2 Note 3 Time Time...
Page 150: Configuration Of A/D Converter
CHAPTER 9 A/D CONVERTER Figure 9-2 shows the block diagram of A/D converter. Figure 9-2. Block Diagram of A/D Converter ANI0/P20/TI000 TOH1 Sample & hold circuit ANI1/P21/TI010/ Voltage comparator TO00/INTP0 D/A converter ANI2/X2/P22 ANI3/X1/P23 Successive approximation register (SAR) Controller INTAD A/D conversion result register (ADCR, ADCRH) ADS1...
Page 151 CHAPTER 9 A/D CONVERTER (5) Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the D/A converter, and converts the result, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR).
Page 152: Registers Used By A/D Converter
CHAPTER 9 A/D CONVERTER Registers Used by A/D Converter The A/D converter uses the following six registers. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • 10-bit A/D conversion result register (ADCR) • 8-bit A/D conversion result register (ADCRH) •...
Page 153 CHAPTER 9 A/D CONVERTER Figure 9-3. Format of A/D Converter Mode Register (ADM) Address: FF80H After reset: 00H Symbol <7> <0> ADCS ADCE ADCS A/D conversion operation control Stops conversion operation Note 1 Starts conversion operation Reference Sampling Conversion = 8 MHz = 10 MHz Note 3 Note 4...
Page 154 CHAPTER 9 A/D CONVERTER Notes 3. Set the sampling time as follows. • V ≥ 4.5 V: µ s or more µ • V ≥ 4.0 V: s or more µ • V ≥ 2.85 V: s or more • V ≥...
Page 155 CHAPTER 9 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 9-5.
Page 156 CHAPTER 9 A/D CONVERTER (4) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit resolution result. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation makes ADCRH undefined.
Page 157: A/D Converter Operations
CHAPTER 9 A/D CONVERTER A/D Converter Operations 9.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). µ <2> Set ADCE to 1 and wait for 1 s or longer. <3>...
Page 158 CHAPTER 9 A/D CONVERTER Figure 9-10. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result ADCR, Conversion ADCRH result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 159: Input Voltage And Conversion Results
CHAPTER 9 A/D CONVERTER 9.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
Page 160: A/D Converter Operation Mode
CHAPTER 9 A/D CONVERTER 9.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register...
Page 161 CHAPTER 9 A/D CONVERTER The setting method is described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
Page 162: How To Read A/D Converter Characteristics Table
CHAPTER 9 A/D CONVERTER How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 163 CHAPTER 9 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
Page 164: Cautions For A/D Converter
CHAPTER 9 A/D CONVERTER Cautions for A/D Converter (1) Supply current in STOP mode To satisfy the DC characteristics of supply current in STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 before executing the STOP instruction. (2) Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage.
Page 165 CHAPTER 9 A/D CONVERTER (5) ANI0/P20 to ANI3/P23 <1> The analog input pins (ANI0 to ANI3) are also used as I/O port pins (P20 to P23). When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access P20 to P23 while conversion is in progress;...
Page 166 CHAPTER 9 A/D CONVERTER (8) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the µ ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0.
Page 167: Chapter 10 Interrupt Functions
CHAPTER 10 INTERRUPT FUNCTIONS 10.1 Interrupt Function Types There are two types of interrupts: maskable interrupts and resets. • Maskable interrupts These interrupts undergo mask control. When an interrupt request occurs, the standby release signal occurs, and if an interrupt can be acknowledged then the program corresponding to the address written in the vector table address is executed (vector interrupt servicing).
Page 168 CHAPTER 10 INTERRUPT FUNCTIONS Table 10-1. Interrupt Sources Note 1 Interrupt Type Priority Interrupt Source Internal/ Vector Table Basic External Address Configuration Name Trigger Note 2 Type Note 3 Maskable INTLVI Low-voltage detection Internal 0006H INTP0 Pin input edge detection External 0008H INTP1...
Page 169: Interrupt Function Control Registers
CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (B) External maskable interrupt Internal bus External interrupt mode register (INTM0) Vector table address generator Edge Interrupt detector...
Page 170 CHAPTER 10 INTERRUPT FUNCTIONS Table 10-2. Interrupt Request Signals and Corresponding Flags Interrupt Request Signal Interrupt Request Flag Interrupt Mask Flag INTLVI LVIIF LVIMK INTP0 PIF0 PMK0 INTP1 PIF1 PMK1 INTTMH1 TMIFH1 TMMKH1 INTTM000 TMIF000 TMMK000 INTTM010 TMIF010 TMMK010 INTAD ADIF ADMK (1) Interrupt request flag register 0 (IF0)
Page 171 CHAPTER 10 INTERRUPT FUNCTIONS (2) Interrupt mask flag register 0 (MK0) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 is set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets MK0 to FFH. Figure 10-3.
Page 172: Interrupt Servicing Operation
CHAPTER 10 INTERRUPT FUNCTIONS Caution 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag (××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will enable interrupts.
Page 173 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-6 shows the algorithm of interrupt request acknowledgment. When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches.
Page 174: Multiple Interrupt Servicing
CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-8. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) 8 clocks Clock Interrupt Saving PSW and PC, jump servicing MOV A, r to interrupt servicing program Interrupt If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment processing starts after the next instruction is executed.
Page 175 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-9. Example of Multiple Interrupts (1/2) Example 1. Multiple interrupts are acknowledged INTxx servicing INTyy servicing Main processing IE = 0 IE = 0 INTxx INTyy RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated. Before each interrupt request acknowledgement, the EI instruction is issued, the interrupt mask is released, and the interrupt request acknowledgement enable state is set.
Page 177: Chapter 11 Standby Function
CHAPTER 11 STANDBY FUNCTION 11.1 Standby Function and Configuration 11.1.1 Standby function Table 11-1. Relationship Between Operation Clocks in Each Operation Status Status Low-Speed Internal Oscillator System Clock Clock Supplied to Peripheral Note 1 Note 2 Hardware Operation Mode LSRSTOP = 0 LSRSTOP = 1 Reset Stopped...
Page 178 CHAPTER 11 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, select the HALT mode if processing must be immediately started by an interrupt request when the Note operation stop time...
Page 179: Registers Used During Standby
CHAPTER 11 STANDBY FUNCTION 11.1.2 Registers used during standby The oscillation stabilization time after the standby mode is released is controlled by the oscillation stabilization time select register (OSTS). Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATORS. (1) Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released.
Page 180: Standby Function Operation
CHAPTER 11 STANDBY FUNCTION 11.2 Standby Function Operation 11.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operating statuses in the HALT mode are shown below. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag clear, the standby mode is immediately cleared if set.
Page 181 CHAPTER 11 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed.
Page 182 CHAPTER 11 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 11-3.
Page 183: Stop Mode
CHAPTER 11 STANDBY FUNCTION 11.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
Page 184 CHAPTER 11 STANDBY FUNCTION (2) STOP mode release Figure 11-4. Operation Timing When STOP Mode Is Released <1> If high-speed internal oscillation clock or external input clock is selected as system clock to be supplied STOP mode is released. STOP mode System clock oscillation CPU clock...
Page 185 CHAPTER 11 STANDBY FUNCTION (a) Release by unmasked interrupt request Note When an unmasked interrupt request (8-bit timer H1 , low-voltage detector, external interrupt request) is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 186 CHAPTER 11 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 11-6. STOP Mode Release by Reset signal generation (1) If CPU clock is high-speed internal oscillation clock or external input clock STOP instruction...
Page 187: Chapter 12 Reset Function
CHAPTER 12 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer overflows (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 188 CHAPTER 12 RESET FUNCTION Figure 12-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF LVIRF Clear Reset signal of WDT Clear Reset signal to LVIM/LVIS register RESET Reset signal of POC Internal reset signal Reset signal of LVI Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit.
Page 189 CHAPTER 12 RESET FUNCTION Figure 12-2. Timing of Reset by RESET Input <1> With high-speed internal oscillation clock or external clock input High-speed internal oscillation clock or external clock input Normal operation Reset period CPU clock Normal operation (reset processing, CPU clock) in progress (oscillation stops) RESET...
Page 190 CHAPTER 12 RESET FUNCTION Figure 12-3. Timing of Reset by Overflow of Watchdog Timer <1> With high-speed internal oscillation clock or external clock input High-speed internal oscillation clock or external clock input Reset period Normal operation Normal operation (reset processing, CPU clock) CPU clock (oscillation stops) in progress...
Page 191 CHAPTER 12 RESET FUNCTION Figure 12-4. Reset Timing by RESET Input in STOP Mode <1> With high-speed internal oscillation clock or external clock input STOP instruction is executed. High-speed internal oscillation clock or external clock input Normal Reset period Stop status Normal operation (reset processing, CPU clock) operation CPU clock...
Page 192 CHAPTER 12 RESET FUNCTION Table 12-1. Hardware Statuses After Reset Acknowledgment (1/2) Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Undefined Data memory Note 2...
Page 193 CHAPTER 12 RESET FUNCTION Table 12-1. Hardware Statuses After Reset Acknowledgment (2/2) Hardware Status After Reset Note Reset function Reset control flag register (RESF) Note Low-voltage detector Low-voltage detection register (LVIM) Note Low-voltage detection level select register (LVIS) Interrupt Request flag registers (IF0) Mask flag registers (MK0) External interrupt mode registers (INTM0) Flash memory...
Page 194: Register For Confirming Reset Source
CHAPTER 12 RESET FUNCTION 12.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0S/KU1+. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset signal generation by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Page 195: Chapter 13 Power-On-Clear Circuit
CHAPTER 13 POWER-ON-CLEAR CIRCUIT 13.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (V = 2.1 V ±0.1 V), and generates internal reset signal ) and detection voltage (V when V <...
Page 196: Configuration Of Power-On-Clear Circuit
CHAPTER 13 POWER-ON-CLEAR CIRCUIT 13.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 13-1. Figure 13-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 13.3 Operation of Power-on-Clear Circuit = 2.1 V ±0.1 V) are compared, In the power-on-clear circuit, the supply voltage (V ) and detection voltage (V...
Page 197: Cautions For Power-On-Clear Circuit
CHAPTER 13 POWER-ON-CLEAR CIRCUIT 13.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 198 CHAPTER 13 POWER-ON-CLEAR CIRCUIT Figure 13-3. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Reset processing by low-voltage detector Power-on clear/external reset generated...
Page 199: Chapter 14 Low-Voltage Detector
CHAPTER 14 LOW-VOLTAGE DETECTOR 14.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V < V •...
Page 200: Registers Controlling Low-Voltage Detector
CHAPTER 14 LOW-VOLTAGE DETECTOR 14.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detect register (LVIM) • Low-voltage detection level select register (LVIS) (1) Low-voltage detect register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 201 CHAPTER 14 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. Note Reset signal generation clears this register to 00H Figure 14-3. Format of Low-Voltage Detection Level Select Register (LVIS) Note Address: FF51H, After reset: 00H Symbol...
Page 202: Operation Of Low-Voltage Detector
CHAPTER 14 LOW-VOLTAGE DETECTOR 14.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. • Used as reset Compares the supply voltage (V ) and detection voltage (V ), and generates an internal reset signal when ≥...
Page 203 CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (V LVI detection voltage POC detection voltage <2> Time LVIMK flag (set by software) <1> Note 1 LVION flag Not cleared Not cleared (set by software) <3>...
Page 204 CHAPTER 14 LOW-VOLTAGE DETECTOR (2) When used as interrupt • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS).
Page 205 CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (V LVI detection voltage POC detection voltage Time <2> LVIMK flag (set by software) <1> Note 1 <7> Cleared by software LVION flag (set by software) <3>...
Page 206: Cautions For Low-Voltage Detector
CHAPTER 14 LOW-VOLTAGE DETECTOR 14.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. <1>...
Page 207 CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-6. Example of Software Processing After Release of Reset (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Note ; Check reset source Initialization Initialization of ports processing <1>...
Page 208 CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-6. Example of Software Processing After Release of Reset (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Power-on-clear/external reset generated Reset processing by low-voltage detector...
Page 209: Chapter 15 Option Byte
CHAPTER 15 OPTION BYTE 15.1 Functions of Option Byte The address 0080H of the flash memory of the 78K0S/KU1+ is an option byte area. When power is supplied or when starting after a reset, the option byte is automatically referenced, and settings for the specified functions are performed.
Page 210: Format Of Option Byte
CHAPTER 15 OPTION BYTE 15.2 Format of Option Byte Format of option bytes is shown below. Figure 15-2. Format of Option Byte (1/2) Address: 0080H DEFOSTS1 DEFOSTS0 RMCE OSCSEL1 OSCSEL0 LIOCP DEFOSTS1 DEFOSTS0 Oscillation stabilization time on power application or after reset release µ...
Page 211: Caution When The Reset Pin Is Used As An Input-Only Port Pin (P34)
CHAPTER 15 OPTION BYTE Figure 15-2. Format of Option Byte (2/2) LIOCP Low-speed internal oscillates Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit) Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit) Cautions 1.
Page 212: Chapter 16 Flash Memory
CHAPTER 16 FLASH MEMORY 16.1 Features The internal flash memory of the 78K0S/KU1+ has the following features. Erase/write even without preparing a separate dedicated power supply Capacity: 1/2/4 KB • Erase unit: 1 block (256 bytes) • Write unit: 1 block (at onboard/offboard programming time), 1 byte (at self programming time) Rewriting method •...
Page 213: Memory Configuration
CHAPTER 16 FLASH MEMORY 16.2 Memory Configuration The 1/2/4 KB internal flash memory area is divided into 4/8/16 blocks and can be programmed/erased in block units. All the blocks can also be erased at once, by using a dedicated flash memory programmer. Figure 16-1.
Page 214: Functional Outline
CHAPTER 16 FLASH MEMORY Table 16-1. Rewrite Method Rewrite Method Functional Outline Operation Mode On-board programming Flash memory can be rewritten after the device is mounted on the Flash memory target system, by using a dedicated flash memory programmer. programming mode Off-board programming Flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash memory programmer and a...
Page 215: Programming Environment
CHAPTER 16 FLASH MEMORY 16.5 Programming Environment The environment required for writing a program to the flash memory is illustrated below. <R> Figure 16-2. Environment for Writing Program to Flash Memory (FlashPro4/FlashPro5/QB-MINI2) QB-MINI2 FlashPro5 RESET RS-232-C FlashPro4 Note SI/RxD Axxxx Bxxxxx Cxxxxxx SO/TxD...
Page 216 CHAPTER 16 FLASH MEMORY <R> Table 16-2. Wiring Between 78K0S/KU1+ and FlashPro4/FlashPro5/QB-MINI2 FlashPro4/FlashPro5/QB-MINI2 Connection Pin 78K0S/KU1+ Connection Pin Pin Name Pin Function Pin Name Pin No. Note 1 Output Clock to 78K0S/KU1+ X1/P23/ANI3 Notes 1, 2 FLMD0 Output On-board mode signal Notes 1, 2 SI/RxD Input...
Page 217: Processing Of Pins On Board
CHAPTER 16 FLASH MEMORY 16.6 Processing of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 218: Reset Pin
CHAPTER 16 FLASH MEMORY <R> Figure 16-5. PG-FP5 GUI Software Setting Example Set oscillation frequency Click (Standard tab in Device setup window) (Main window) Table 16-4. Oscillation Frequency and PG-FP5 GUI Software Setting Value Example Oscillation Frequency PG-FP5 GUI Software Setting Value Example (Communication Frequency) 2 MHz ≤...
Page 219: Port Pins
CHAPTER 16 FLASH MEMORY Figure 16-6. Signal Collision (RESET Pin) 78K0S/KU1+ Dedicated flash programmer Signal collision connection signal RESET Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer.
Page 220: On-Board And Off-Board Flash Memory Programming
CHAPTER 16 FLASH MEMORY 16.7 On-Board and Off-Board Flash Memory Programming 16.7.1 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0S/KU1+ in the flash memory programming mode. When the 78K0S/KU1+ are connected to the flash memory programmer and a communication command is transmitted to the microcontroller, the microcontroller is set in the flash memory programming mode.
Page 221: Security Settings
CHAPTER 16 FLASH MEMORY Table 16-6. Response Name Command Name Function Acknowledges command/data. Acknowledges illegal command/data. 16.7.3 Security settings The operations shown below can be prohibited using the security setting command. • Batch erase (chip erase) is prohibited Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is prohibited.
Page 222: Flash Memory Programming By Self Programming
CHAPTER 16 FLASH MEMORY Table 16-8 shows the relationship between the security setting and the operation in each programming mode. Table 16-8. Relationship Between Security Setting and Operation In Each Programming Mode Programming Mode On-Board/Off-Board Programming Self Programming Security Setting Security Setting Security Operation Security Setting...
Page 223 Figure 16-8. Block Diagram of Self Programming Internal bus Flash programming command Protect byte register (FLCMD) Flash programming mode Flash protect command PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 FLCMD2 FLCMD1 FLCMD0 Self programming mode control register (FLPMC) register (PFCMD) setting sequencer Self programming mode setting register HALT signal Self programming command execution...
Page 224 CHAPTER 16 FLASH MEMORY Figure 16-9. Self Programming State Transition Diagram User program Operation setting Normal mode Specific sequence Operation setting Register for Self programming mode self programming Self programming command Self programming execution by HALT instruction command completion/error Flash memory control block (hardware) Operation reference Self programming...
Page 225: Cautions On Self Programming Function
CHAPTER 16 FLASH MEMORY 16.8.2 Cautions on self programming function • No instructions can be executed while a self programming command is being executed. Therefore, clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming.
Page 226 CHAPTER 16 FLASH MEMORY This register is set with an 8-bit memory manipulation instruction. Reset signal generation makes the contents of this register undefined. Figure 16-10. Format of Flash Programming Mode Control Register (FLPMC) Note 1 Note 2 Address: FFA2H After reset: Undefined Symbol FLPMC...
Page 227 CHAPTER 16 FLASH MEMORY (2) Flash protect command register (PFCMD) If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an operation to write the flash programming mode control register (FLPMC) may have a serious effect on the system.
Page 228 CHAPTER 16 FLASH MEMORY Figure 16-12. Format of Flash Status Register (PFS) Address: FFA1H After reset: 00H Symbol WEPRERR VCERR FPRERR 1. Operating conditions of FPRERR flag <Setting conditions> • If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to write a specific value (A5H) to FLPMC •...
Page 229 CHAPTER 16 FLASH MEMORY (4) Flash programming command register (FLCMD) This register is used to specify whether the flash memory is erased, written, or verified in the self-programming mode. This register is set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 230 CHAPTER 16 FLASH MEMORY (5) Flash address pointers H and L (FLAPH and FLAPL) These registers are used to specify the start address of the flash memory when the memory is erased, written, or verified in the self-programming mode. FLAPH and FLAPL consist of counters, and they are incremented until the values match with those of FLAPHC and FLAPLC when the programming command is not executed.
Page 231 CHAPTER 16 FLASH MEMORY (7) Flash write buffer register (FLW) This register is used to store the data to be written to the flash memory. This register is set with an 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 16-16.
Page 232: Example Of Shifting Normal Mode To Self Programming Mode
CHAPTER 16 FLASH MEMORY Figure 16-17. Format of Protect Byte (2/2) µ • PD78F9202 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 Status Blocks 15 to 0 are protected. Blocks 13 to 0 are protected. Blocks 14 and 15 can be written or erased. Blocks 11 to 0 are protected.
Page 233 CHAPTER 16 FLASH MEMORY Figure 16-18. Example of Shifting to Self Programming Mode Shift to self programming mode <1> Disable interrupts (by setting MK0 to FFH and executing DI ; When interrupt function is used instruction) <2> Clear FLCMD (FLCMD=00H). <3>...
Page 234 CHAPTER 16 FLASH MEMORY An example of the program that shifts the mode to self programming mode is shown below. ;---------------------------- ;START ;---------------------------- MK0,#11111111B ; Masks all interrupts FLCMD,#00H ; Clear FLCMD register ; Configure settings so that the CPU clock ≥ 1 MHz ModeOnLoop: PFS,#00H ;...
Page 235: Example Of Shifting Self Programming Mode To Normal Mode
CHAPTER 16 FLASH MEMORY 16.8.5 Example of shifting self programming mode to normal mode The operating mode must be returned from self programming mode to normal mode after performing self programming. An example of shifting to normal mode is explained below. <1>...
Page 236 CHAPTER 16 FLASH MEMORY Figure 16-19. Example of Shifting to Normal Mode Shift to normal mode <1> Clear FLCMD (FLCMD=00H) <2> Clear PFS PFCMD = A5H FLPMC = 00H (set value) ; Set value is invalid <3> FLPMC = 0FFH (inverted set value) FLPMC = 00H (set value) ;...
Page 237 CHAPTER 16 FLASH MEMORY An example of a program that shifts the mode to normal mode is shown below. ;---------------------------- ;START ;---------------------------- FLCMD,#00H ; Clear FLCMD register ModeOffLoop: PFS,#00H ; Clears flash status register PFCMD,#0A5H ; PFCMD register control FLPMC,#00H ;...
Page 238: Example Of Block Erase Operation In Self Programming Mode
CHAPTER 16 FLASH MEMORY 16.8.6 Example of block erase operation in self programming mode An example of the block erase operation in self programming mode is explained below. <1> Set 03H (block erase) to the flash program command register (FLCMD). <2>...
Page 239 CHAPTER 16 FLASH MEMORY Figure 16-20. Example of Block Erase Operation in Self Programming Mode Block erasure <1> Set erase command (FLCMD = 03H) <2> Set no. of block to be erased to FLAPH <3> Set FLAPL to 00H <4> Set the same value as that of FLAPH to FLAPHC <5>...
Page 240 CHAPTER 16 FLASH MEMORY An example of a program that performs a block erase in self programming mode is shown below. ;---------------------------- ;START ;---------------------------- FlashBlockErase: FLCMD,#03H ; Sets flash control command (block erase) FLAPH,#07H ; Sets number of block to be erased (block 7 is specified here) FLAPL,#00H ;...
Page 241: Example Of Block Blank Check Operation In Self Programming Mode
CHAPTER 16 FLASH MEMORY 16.8.7 Example of block blank check operation in self programming mode An example of the block blank check operation in self programming mode is explained below. <1> Set 04H (block blank check) to the flash program command register (FLCMD). <2>...
Page 242 CHAPTER 16 FLASH MEMORY Figure 16-21. Example of Block Blank Check Operation in Self Programming Mode Block blank check <1> Set block blank check command (FLCMD = 04H) <2> Set no. of block for blank check to FLAPH <3> Set FLAPL to 00H <4>...
Page 243 CHAPTER 16 FLASH MEMORY An example of a program that performs a block blank check in self programming mode is shown below. ;---------------------------- ;START ;---------------------------- FlashBlockBlankCheck: FLCMD,#04H ; Sets flash control command (block blank check) FLAPH,#07H ; Sets number of block for blank check (block 7 is specified ;...
Page 244: Example Of Byte Write Operation In Self Programming Mode
CHAPTER 16 FLASH MEMORY 16.8.8 Example of byte write operation in self programming mode An example of the byte write operation in self programming mode is explained below. <1> Set 05H (byte write) to the flash program command register (FLCMD). <2>...
Page 245 CHAPTER 16 FLASH MEMORY Figure 16-22. Example of Byte Write Operation in Self Programming Mode Byte write <1> Set byte write command (FLCMD = 05H) <2> Set no. of block to be written, to FLAPH <3> Set address at which data is to be written, to FLAPL <4>...
Page 246 CHAPTER 16 FLASH MEMORY An example of a program that performs a byte write in self programming mode is shown below. ;---------------------------- ;START ;---------------------------- FlashWrite: FLCMD,#05H ; Sets flash control command (byte write) FLAPH,#07H ; Sets address to which data is to be written, with ;...
Page 247: Example Of Internal Verify Operation In Self Programming Mode
CHAPTER 16 FLASH MEMORY 16.8.9 Example of internal verify operation in self programming mode An example of the internal verify operation in self programming mode is explained below. • Internal verify 1 <1> Set 01H (internal verify 1) to the flash program command register (FLCMD). <2>...
Page 248 CHAPTER 16 FLASH MEMORY Figure 16-23. Example of Internal Verify Operation in Self Programming Mode Internal verify 1 <1> Set internal verify 1 command (FLCMD = 01H) <2> Set No. of block for internal verify, to FLAPH <3> Sets FLAPL to 00H <4>...
Page 249 CHAPTER 16 FLASH MEMORY Figure 16-24. Example of Internal Verify Operation in Self Programming Mode Internal verify 2 <1> Set internal verify 2 command (FLCMD = 02H) <2> Set No. of block for internal verify, to FLAPH <3> Sets FLAPL to the start address <4>...
Page 250 CHAPTER 16 FLASH MEMORY An example of a program that performs an internal verify in self programming mode is shown below. • Internal verify 1 ;---------------------------- ;START ;---------------------------- FlashVerify: FLCMD,#01H ; Sets flash control command (internal verify 1) FLAPH,#07H ; Set the number of block for which internal verify is ;...
Page 251: Examples Of Operation When Command Execution Time Should Be Minimized In Self Programming Mode
CHAPTER 16 FLASH MEMORY 16.8.10 Examples of operation when command execution time should be minimized in self programming mode Examples of operation when the command execution time should be minimized in self programming mode are explained below. (1) Erasure to blank check <1>...
Page 252 CHAPTER 16 FLASH MEMORY An example of a program when the command execution time (from erasure to black check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- MK0,#11111111B ; Masks all interrupts FLCMD,#00H ; Clears FLCMD register ;...
Page 253 CHAPTER 16 FLASH MEMORY FLAPLC,#0FFH ; Fixes FLAPLC to “FFH” WDTE,#0ACH ; Clears & restarts WDT HALT ; Self programming is started A,PFS A,#00H $StatusError ; Checks blank check error ; Performs abnormal termination processing when an error ; occurs. FLCMD,#00H ;...
Page 254 CHAPTER 16 FLASH MEMORY (2) Write to internal verify <1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <2> Specification of source data for write <3> Execution of byte write → Error check (<1> to <10> in 16.8.8) <4>...
Page 255 CHAPTER 16 FLASH MEMORY An example of a program when the command execution time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- MK0,#11111111B ; Masks all interrupts FLCMD,#00H ; Clears FLCMD register ;...
Page 256 CHAPTER 16 FLASH MEMORY INCW ; Address at which data is to be written + 1 FlashWriteLoop FlashVerify: MOVW HL,#WriteAdr ; Sets verify address FLCMD,#02H ; Sets flash control command (internal verify 2) FLAPH,A ; Sets verify start address FLAPL,A ;...
Page 257: Examples Of Operation When Interrupt-Disabled Time Should Be Minimized In Self Programming Mode
CHAPTER 16 FLASH MEMORY ;--------------------------------------------------------------------- ;END (normal termination processing) ;--------------------------------------------------------------------- StatusNormal: ;--------------------------------------------------------------------- ; Data to be written ;--------------------------------------------------------------------- DataAdrTop: DataAdrBtm: ;--------------------------------------------------------------------- Remark Internal verify 2 is used in the above program example. Use internal verify 1 to verify s whole block. 16.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode Examples of operation when the interrupt-disabled time should be minimized in self programming mode are explained below.
Page 258 CHAPTER 16 FLASH MEMORY Figure 16-27. Example of Operation When Interrupt-Disabled Time Should Be Minimized (from Erasure to Blank Check) Erasure to blank check Figure 16-20 <1> Specify block erase command <1> to <5> <2> Shift to self programming Figure 16-18 mode <1>...
Page 259 CHAPTER 16 FLASH MEMORY An example of a program when the interrupt-disabled time (from erasure to blank check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- FlashBlockErase: ; Sets erase command FLCMD,#03H ; Sets flash control command (block erase) FLAPH,#07H ;...
Page 260 CHAPTER 16 FLASH MEMORY CALL !ModeOff ; Shift to normal mode StatusNormal ;--------------------------------------------------------------------- ;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------- StatusError: ;--------------------------------------------------------------------- ;END (normal termination processing) ;--------------------------------------------------------------------- StatusNormal: ;--------------------------------------------------------------------- ;Processing to shift to self programming mode ;---------------------------------------------------------------------...
Page 261 CHAPTER 16 FLASH MEMORY FLPMC,#00H ; FLPMC register control (sets value) FLPMC,#0FFH ; FLPMC register control (inverts set value) FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ;...
Page 262 CHAPTER 16 FLASH MEMORY (2) Write to internal verify <1> Specification of source data for write <2> Specification of byte write command (<1> to <4> in 16.8.8) <3> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <4>...
Page 263 CHAPTER 16 FLASH MEMORY Figure 16-28. Example of Operation When Interrupt-Disabled Time Should Be Minimized (from Write to Internal Verify) Write to internal verify <1> Set source data for write Figure 16-22 <2> Specify byte write command <1> to <4> <3>...
Page 264 CHAPTER 16 FLASH MEMORY An example of a program when the interrupt-disabled time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- ; Sets write command FlashWrite: MOVW HL,#DataAdrTop ; Sets address at which data to be written is located MOVW DE,#WriteAdr ;...
Page 265 CHAPTER 16 FLASH MEMORY FlashVerify: MOVW HL,#WriteAdr ; Sets verify address FLCMD,#02H ; Sets flash control command (internal verify 2) FLAPH,A ; Sets verify start address FLAPL,A ; Sets verify start address FLAPHC,A ; Sets verify end address FLAPLC,A ; Sets verify end address CALL !ModeOn ;...
Page 266 CHAPTER 16 FLASH MEMORY ; Configure settings so that the CPU clock ≥ 1 MHz ModeOnLoop: PFS,#00H ; Clears flash status register PFCMD,#0A5H ; PFCMD register control FLPMC,#01H ; FLPMC register control (sets value) FLPMC,#0FEH ; FLPMC register control (inverts set value) FLPMC,#01H ;...
Page 267 CHAPTER 16 FLASH MEMORY DataAdrBtm: ;--------------------------------------------------------------------- Remark Internal verify 2 is used in the above program example. Use internal verify 1 to verify s whole block. User’s Manual U18172EJ2V0UD...
Page 268: Chapter 17 On-Chip Debug Function
Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is not liable for problems occurring when the on-chip debug function is used.
Page 269: Connection Of Intp1 Pin
CHAPTER 17 ON-CHIP DEBUG FUNCTION Note 5. The INTP1 pin is used for communication between QB-MINI2 and the target device during debugging. When debugging is performed with QB-MINI2, therefore, the INTP1 pin and its alternate-function pin cannot be used. For INTP1 pin connection, refer to 17.1.1 Connection of INTP1 pin.
Page 270: Connection Of X1 And X2 Pins
CHAPTER 17 ON-CHIP DEBUG FUNCTION Figure 17-4. Circuit Connection for the Case Where QB-MINI2 Is Used for Debugging and Debugging of INTP1 Pin Is Performed Only with Real Machine Target connector 1 kΩ Target device INTP INTP1 External device I/O to INTP1 * Jumper setting When debugging with QB-MINI2 connected: 1-2 shorted...
Page 271: Securing Of User Resources
CHAPTER 17 ON-CHIP DEBUG FUNCTION 17.2 Securing of user resources The user must prepare the following to perform communication between QB-MINI2 and the target device and implement each debug function. For details of the setting, refer to QB-MINI2 User’s Manual (U18371E). •...
Page 272: Chapter 18 Instruction Set Overview
CHAPTER 18 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the 78K0S/KU1+. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 18.1 Operation 18.1.1 Operand identifiers and description methods Operands are described in “Operand”...
Page 273: Description Of "Operation" Column
CHAPTER 18 INSTRUCTION SET OVERVIEW 18.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 274: Operation List
CHAPTER 18 INSTRUCTION SET OVERVIEW 18.2 Operation List Mnemonic Operand Bytes Clocks Operation Flag AC CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte A ← r Note 1 A, r r ← A Note 1 r, A A ←...
Page 275 CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY rp ← word MOVW rp, #word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX AX ← rp Note AX, rp rp ← AX Note rp, AX AX ↔...
Page 276 CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY A, CY ← A − byte − CY × × × SUBC A, #byte (saddr), CY ← (saddr) − byte − CY × × × saddr, #byte A, CY ←...
Page 277 CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY A − byte × × × A, #byte (saddr) − byte × × × saddr, #byte A − r × × × A, r A − (saddr) ×...
Page 278 CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) CALL !addr16 PC ← addr16, SP ← SP − 2 (SP − 1) ← (PC + 1) , (SP −...
Page 279: Instructions Listed By Addressing Type
CHAPTER 18 INSTRUCTION SET OVERVIEW 18.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr !addr16 [DE] [HL] $addr16 None [HL + byte]...
Page 280 CHAPTER 18 INSTRUCTION SET OVERVIEW (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW SUBW MOVW MOVW MOVW CMPW XCHW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL.
Page 281 CHAPTER 18 INSTRUCTION SET OVERVIEW (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic instructions CALL CALLT Compound instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U18172EJ2V0UD...
Page 282: Chapter 19 Electrical Specifications
CHAPTER 19 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +0.3 −0.3 to V Note Input voltage P20 to P23, P32, P34, P40, P43 + 0.3 −0.3 to V Note Output voltage + 0.3...
Page 283 CHAPTER 19 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V Note 1 <R> X1 Oscillator Characteristics (T = 2.0 to 5.5 V = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic Oscillation 10.0 Note 2 resonator frequency (f Crystal Oscillation 10.0...
Page 284 CHAPTER 19 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V Note 1 High-Speed Internal Oscillator Characteristics (T = 2.0 to 5.5 V User’s Manual U18172EJ2V0UD...
Page 285 CHAPTER 19 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V Note DC Characteristics (T = 2.0 to 5.5 V = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.0 V ≤ V ≤ 5.5 V Output current, high Per pin –5 4.0 V ≤...
Page 286 CHAPTER 19 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V Note 1 DC Characteristics (T = 2.0 to 5.5 V = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 3 Supply Crystal/ceramic = 10 MHz When A/D converter is stopped 12.2 = 5.0 V ±10% Note 2...
Page 287 CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Characteristics = −40 to +85°C, V Note 1 Basic operation (T = 2.0 to 5.5 V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ 4.0 V ≤ V ≤ 5.5 V Cycle time (minimum Crystal/ceramic oscillation instruction execution time) clock, external clock input...
Page 288 CHAPTER 19 ELECTRICAL SPECIFICATIONS vs. V (Crystal/Ceramic Oscillation Clock, External Clock Input) Guaranteed operation range 0.33 Supply voltage V vs. V (High-speed internal oscillator Clock) 4.22 Guaranteed operation range 0.95 0.47 0.23 Supply voltage V User’s Manual U18172EJ2V0UD...
Page 289 CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Timing Test Points (Excluding X1 Input) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing X1 input TI000 Timing TI000 Interrupt Input Timing INTL INTH INTP0, INTP1 RESET Input Timing RESET User’s Manual U18172EJ2V0UD...
Page 290 CHAPTER 19 ELECTRICAL SPECIFICATIONS = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V Note 1 Note 2 A/D Converter Characteristics (T = 0 V (1) A/D converter basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution µ 4.5 V ≤...
Page 291 CHAPTER 19 ELECTRICAL SPECIFICATIONS = −40 to +85°C) POC Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage µ : 0 V → 2.1 V Power supply rise time Note 1 Response delay time 1 When power supply rises, after reaching PTHD detection voltage (MAX.) Note 2...
Page 292 CHAPTER 19 ELECTRICAL SPECIFICATIONS = −40 to +85°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage LVI0 LVI1 LVI2 LVI3 LVI4 3.15 3.45 LVI5 2.95 3.25 LVI6 2.85 LVI7 LVI8 2.25 2.35 2.45 LVI9 Note 1 Response time Minimum pulse width Note 2...
Page 293 CHAPTER 19 ELECTRICAL SPECIFICATIONS = –40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V Flash Memory Programming Characteristics (T = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current = 5.5 V = −40 to +85°C Note 1 Erasure count 1000...
Page 294: Chapter 20 Package Drawing
CHAPTER 20 PACKAGE DRAWING 10-PIN PLASTIC SSOP (5.72 mm (225)) detail of lead end (UNIT:mm) ITEM DIMENSIONS 3.60± 0.10 0.50 0.65 (T.P.) ± NOTE 0.24 0.08 0.10 ± 0.05 Each lead centerline is located within 0.13 mm 1.45 MAX. of its true position (T.P.) at maximum material ±...
Page 295: Chapter 21 Recommended Soldering Conditions
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Cautions 1. Products with –A at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 21-1. Surface Mounting Type Soldering Conditions •...
Page 296: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the 78K0S/KU1+. Figure A-1 shows development tools. • Compatibility with PC98-NX series Unless stated otherwise, products which are supported by IBM PC/AT and compatibles can also be used with the PC98-NX series.
Page 297 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools (1/2) (1) When using the in-circuit emulator QB-78K0SKX1 <R> Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger Note 3 • C compiler package • System simulator •...
Page 298 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools (2/2) (2) When using the on-chip debug emulator with programming function QB-MINI2 <R> Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger Note 4 • C compiler package •...
Page 299: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S This is a package that bundles the software tools required for development of the 78K/0S Series. Software package The following tools are included. Note 1 Note 2 Note 3 RA78K0S, CC78K0S, ID78K0S-NS, SM+ for 78K0S/Kx1+ , SM78K0S , and device files µ...
Page 300: Control Software
APPENDIX A DEVELOPMENT TOOLS Notes 1. DF789234 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-QB and SM+ for 78K0S/Kx1+. CC78K0S-L is not included in the software package (SP78K0S). ×××× in the part number differs depending on the host machine and operating system to be used. Remark µ...
Page 301: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) <R> A.5.1 When using in-circuit emulator QB-78K0SKX1 QB-78K0KX1 This in-circuit emulator serves to debug hardware and software when developing application In-circuit emulator systems using the 78K0S/Kx1+. It supports to the integrated debugger (ID78K0-QB). This emulator should be used in combination with a power supply unit and emulation probe, and the USB is used to connect this emulator to the host machine.
Page 302: Appendix B Notes On Designing Target System
APPENDIX B NOTES ON DESIGNING TARGET SYSTEM This chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the QB-78K0SKX1 is used. For the package drawings of the target connector, exchange adapter, and emulation probe, see the following website.
Page 303 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. When using the 78K0S/Kx1+ target cable (single track) Top view Top view Unit : mm Unit : mm 2.54 2.54 2.54 2.54 : A interval pin header → More than 2.54mm : A interval pin header →...
Page 304: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Index (Register Name) 8-bit A/D conversion result register (ADCRH) … 156 8-bit timer H compare register 01 (CMP01) … 124 8-bit timer H compare register 11 (CMP11) … 124 8-bit timer H mode register 1 (TMHMD1) … 125 10-bit A/D conversion result register (ADCR) …...
Page 305 APPENDIX C REGISTER INDEX Port mode control register 2 (PMC2) … 60, 91, 127, 156 Port mode register 2 (PM2) … 59, 91, 127, 156 Port mode register 3 (PM3) … 59 Port mode register 4 (PM4) … 59 Port register 2 (P2) … 60 Port register 3 (P3) …...
Page 306: Register Index (Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (Symbol) ADCR: 10-bit A/D conversion result register … 155 ADCRH: 8-bit A/D conversion result register … 156 ADM: A/D converter mode register … 152 ADS: Analog input channel specification register … 155 CMP01: 8-bit timer H compare register 01 …...
Page 307 APPENDIX C REGISTER INDEX Port register 2 … 60 Port register 3 … 60 Port register 4 … 60 PCC: Processor clock control register … 67 PFCMD: Flash protect command register … 227 PFS: Flash status register … 227 PM2: Port mode register 2 …...
Page 308: Appendix D List Of Cautions
APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document. “Classification (hard/soft)” in table is as follows. Hard: Cautions for microcontroller internal/external hardware Soft: Cautions for software such as register settings or programs (1/15) Function Details of Cautions Page Function...
Page 309 APPENDIX D LIST OF CAUTIONS (2/15) Function Details of Cautions Page Function Main clock OSTS: To set and then release the STOP mode, set the oscillation stabilization time as p. 69 Oscillation follows. stabilization Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time time select set by OSTS register...
Page 310 APPENDIX D LIST OF CAUTIONS (3/15) Function Details of Cautions Page Function 16-bit CR000: 16-bit If the register read period and the input of the capture trigger conflict when CR000 pp. 84, timer/ timer capture/ is used as a capture register, the capture trigger input takes precedence and the event compare read data is undefined.
Page 311 APPENDIX D LIST OF CAUTIONS (4/15) Function Details of Cautions Page Function 16-bit CRC00: The timer operation must be stopped before setting CRC00. pp. 88, timer/ Capture/ event compare control When the clear & start mode entered on a match between TM00 and CR000 is pp.
Page 312 APPENDIX D LIST OF CAUTIONS (5/15) Function Details of Cautions Page Function 16-bit PRM00: When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a pp. 91, timer/ Prescaler mode timer output (TO00). When using P21 as the timer output pin (TO00), it cannot be event register 00 used as the input pin (TI010) of the valid edge.
Page 313 APPENDIX D LIST OF CAUTIONS (6/15) Function Details of Cautions Page Function 16-bit Capture When the CRC001 bit value is 1, capture is not performed in the CR000 register if p. 118 timer/ operation both the rising and falling edges have been selected as the valid edges of the event TI000 pin.
Page 314 APPENDIX D LIST OF CAUTIONS (7/15) Function Details of Cautions Page Function Watchdog WDTM: Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values. p. 140 timer Watchdog timer After reset is released, WDTM can be written only once by an 8-bit memory p.
Page 315 APPENDIX D LIST OF CAUTIONS (8/15) Function Details of Cautions Page Function ADS: Analog Be sure to clear bits 2 to 7 of ADS to 0. p. 155 Converter input channel specification register ADCR: 10-bit When writing to the A/D converter mode register (ADM) and analog input channel p.
Page 316 APPENDIX D LIST OF CAUTIONS (9/15) Function Details of Cautions Page Function ANI0/P20 to The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to p. 165 converter ANI3/P23 P23). When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access P20 to P23 while conversion is in progress;...
Page 317 APPENDIX D LIST OF CAUTIONS (10/15) Function Details of Cautions Page Function Interrupt Interrupt Interrupt requests will be held pending while the interrupt request flag registers p. 174 functions requests are (IF0) or interrupt mask flag registers (MK0) are being accessed. held pending Interrupt Multiple interrupts can be acknowledged even for low-priority interrupts.
Page 318 APPENDIX D LIST OF CAUTIONS (11/15) Function Details of Cautions Page Function µ − Reset For an external reset, input a low level for 2 s or more to the RESET pin. p. 187 function During reset signal generation, the system clock and low-speed internal oscillation p.
Page 319 APPENDIX D LIST OF CAUTIONS (12/15) Function Details of Cautions Page Function Option Oscillation The setting of this option is valid only when the crystal/ceramic oscillation clock is p. 210 byte stabilization selected as the system clock source. No wait time elapses if the high-speed time on power internal oscillation clock or external clock input is selected as the system clock application or...
Page 320 APPENDIX D LIST OF CAUTIONS (13/15) Function Details of Cautions Page Function Self programming processing must be included in the program before performing Flash Self p. 222 self programming. memory programming function No instructions can be executed while a self programming command is being p.
Page 321 78K0S/KU1+ memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is not liable for problems occurring when the on-chip debug function is used. The constants described in the circuit connection example are reference values. If p.
Page 322 295 mended products soldering − For soldering methods and conditions other than those recommended below, p. 295 conditions contact an NEC Electronics sales representative. Do not use different soldering methods together (except for partial heating). p. 295 User’s Manual U18172EJ2V0UD...
Page 323: Appendix E Revision History
APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition Page Description p. 14 Modification of 1.1 Features p. 17 Addition of Note 2 to 5 in 1.4 78K0S/Kx1+ Product Lineup p. 149 9.1 Functions of A/D Converter • Addition of Notes 4 to Table 9-1 Sampling Time and A/D Conversion Time p.
Page 324 Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd. Arcadiastrasse 10 District, Beijing 100083, P.R.China Santa Clara, CA 95050-2554, U.S.A.

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