Registers Controlling 8-Bit Timer/Event Counters 50 And 51 - NEC 78K0 Series User Manual

8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51

The following four registers are used to control 8-bit timer/event counters 50 and 51.
• Timer clock selection register 5n (TCL5n)
• 8-bit timer mode control register 5n (TMC5n)
• Port mode register 1 (PM1) or port mode register 3 (PM3)
• Port register 1 (P1) or port register 3 (P3)
(1) Timer clock selection register 5n (TCL5n)
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input.
TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets TCL5n to 00H.
Remark n = 0, 1
Figure 8-5. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH After reset: 00H
Symbol 7
TCL50 0
TCL502
0
0
0
0
1
1
1
1
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.
Remark f : Peripheral hardware clock frequency
PRS
248
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R/W
6 5
0 0
TCL501 TCL500
0 0 TI50 pin falling edge
0 1 TI50 pin rising edge
1 0 f
PRS
1 1 f /2
PRS
0 0 f /2
PRS
0 1 f /2
PRS
1 0 f /2
PRS
1 1 f /2
PRS
Preliminary User's Manual U17260EJ3V1UD
4 3 2
0 0 TCL502
Count clock selection
f = f =
PRS PRS
2 MHz 5 MHz
2 MHz 5 MHz
1 MHz 2.5 MHz
2
500 kHz 1.25 MHz
6
31.25 kHz 78.13 kHz
8
7.81 kHz 19.53 kHz
13
0.24 kHz 0.61 kHz
1 0
TCL501 TCL500
f = f =
PRS PRS
10 MHz 20 MHz
10 MHz 20 MHz
5 MHz 10 MHz
2.5 MHz 5 MHz
156.25 kHz 312.5 kHz
39.06 kHz 78.13 kHz
1.22 kHz 2.44 kHz