NEC 78K0 Series User Manual page 204

Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Compare Register) (1/2)
(a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 08H, CR01n = 0001H
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n pin input)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
TO0n pin output
This is an application example where the output level of the TO0n pin is to be inverted when the count value has
been captured & cleared.
TM0n is cleared at the rising edge detection of the TI00n pin and it is captured to CR00n at the falling edge
detection of the TI00n pin.
When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is set to 1, the count value of TM0n is
captured to CR00n in the phase reverse to that of the signal input to the TI00n pin, but the capture interrupt signal
(INTTM00n) is not generated. However, the INTTM00n signal is generated when the valid edge of the TI01n pin
is detected. Mask the INTTM00n signal when it is not used.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
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0000H
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0001H
Preliminary User's Manual U17260EJ3V1UD
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