NEC 78K0 Series User Manual page 73

Address Special Function Register (SFR) Name
FF00H Port register 0
FF01H Port register 1
FF02H Port register 2
FF03H Port register 3
FF04H Port register 4
FF05H Port register 5
FF06H Port register 6
FF07H Port register 7
FF08H 10-bit A/D conversion result register
FF09H 8-bit A/D conversion result register
FF0AH Receive buffer register 6
FF0BH Transmit buffer register 6
FF0CH Port register 12
FF0DH Port register 13
FF0EH Port register 14
FF0FH Serial I/O shift register 10
FF10H 16-bit timer counter 00
FF11H
FF12H 16-bit timer capture/compare register 000
FF13H
FF14H 16-bit timer capture/compare register 010
FF15H
FF16H 8-bit timer counter 50
FF17H 8-bit timer compare register 50
FF18H 8-bit timer H compare register 00
FF19H 8-bit timer H compare register 10
FF1AH 8-bit timer H compare register 01
FF1BH 8-bit timer H compare register 11
FF1FH 8-bit timer counter 51
FF20H Port mode register 0
FF21H Port mode register 1
FF22H Port mode register 2
FF23H Port mode register 3
FF24H Port mode register 4
FF25H Port mode register 5
FF26H Port mode register 6
FF27H Port mode register 7
FF28H A/D converter mode register
FF29H Analog input channel specification register
FF2CH Port mode register 12
FF2EH Port mode register 14
FF2FH A/D port configuration register
CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Special Function Register List (1/4)
Symbol
P0
P1
P2
P3
P4
P5
P6
P7
ADCR
ADCRH
RXB6
TXB6
P12
P13
P14
SIO10
TM00
CR000
CR010
TM50
CR50
CMP00
CMP10
CMP01
CMP11
TM51
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
ADM
ADS
PM12
PM14
ADPC
Preliminary User's Manual U17260EJ3V1UD
R/W Manipulatable Bit Unit
1 Bit 8 Bits
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
− −
R
− √
R
− √
R
− √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
− √
R
− −
R
− −
R/W
− −
R/W
− √
R
− √
R/W
− √
R/W
− √
R/W
− √
R/W
− √
R/W
− √
R
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
√ √
R/W
After
Reset
16 Bits
−
00H
−
00H
−
00H
−
00H
−
00H
−
00H
−
00H
−
00H
√
0000H
−
00H
−
FFH
−
FFH
−
00H
−
00H
−
00H
−
00H
√
0000H
√
0000H
√
0000H
−
00H
−
00H
−
00H
−
00H
−
00H
−
00H
−
00H
−
FFH
−
FFH
−
FFH
−
FFH
−
FFH
−
FFH
−
FFH
−
FFH
−
00H
−
00H
−
FFH
−
FFH
−
00H
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