NEC 78K0 Series User Manual page 423

2
For example, the I C transfer clock frequency (f
50 ns is calculated using following expression.
= 1/(88 × 238.7 ns + 200 ns + 50 ns) ≅ 48.1 kHz
f
SCL
SCL0
SCL0
The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection
register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0).
IICX0 IICCL0
Bit 0 Bit 3 Bit 1 Bit 0
CLX0 SMC0 CL01 CL00
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
×
0 1 0
0 1 1 0
0 1 1 1
× ×
1 0
×
1 1 0
1 1 1 0
1 1 1 1
Caution Determine the transfer clock frequency of I
enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change
the transfer clock frequency, clear IICE0 once to 0.
Remarks 1. ×:
don't care
2. f : Peripheral hardware clock frequency
PRS
3. f : External clock frequency from EXSCL0 pin
EXSCL0
CHAPTER 17 SERIAL INTERFACE IIC0
SCL
m × T + t
m/2 × T
t
R
inversion SCL0
Table 17-2. Selection Clock Setting
Selection Clock Transfer Clock
(f )
W
f /2 f
PRS W
f /2 f
PRS W
f /4 f
PRS W
f f
EXSCL0 W
f /2 f
PRS W
f /4 f
PRS W
f f
EXSCL0 W
Setting prohibited
f /2 f
PRS W
f /4 f
PRS W
Setting prohibited
Preliminary User's Manual U17260EJ3V1UD
) when f = f /2 = 4.19 MHz, m = 86, t
W PRS
+ t
R F
t
m/2 × T
F
inversion SCL0
Settable Selection Clock
(f /m) (f ) Range
W W
/44 2.00 to 4.19 MHz
/86 4.19 to 8.38 MHz
/86
/66 6.4 MHz
/24 4.00 to 8.38 MHz
/24
/18 6.4 MHz
/12 4.00 to 4.19 MHz
/12
2
C by using CLX0, SMC0, CL01, and CL00 before
= 200 ns, and t
R
inversion
Operation Mode
Normal mode
(SMC0 bit = 0)
High-speed mode
(SMC0 bit = 1)
High-speed mode
(SMC0 bit = 1)
=
F
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