Operation Of 16-Bit Timer/Event Counters 00 And 01; Interval Timer Operation - NEC 78K0 Series User Manual

7.4 Operation of 16-Bit Timer/Event Counters 00 and 01

7.4.1 Interval timer operation

If bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register (TMC0n) are set to 11 (clear & start
mode entered upon a match between TM0n and CR00n), the count operation is started in synchronization with the
count clock.
When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H and a match interrupt signal
(INTTM00n) is generated. This INTTM00n signal enables TM0n to operate as an interval timer.
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
Count clock
Operable bits
TMC0n3, TMC0n2
Figure 7-17. Basic Timing Example of Interval Timer Operation
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
188
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-16. Block Diagram of Interval Timer Operation
Clear
16-bit counter (TM0n)
CR00n register
N
00
Interval
(N + 1)
Preliminary User's Manual U17260EJ3V1UD
Match signal
N N
11
N
Interval Interval
(N + 1) (N + 1)
INTTM00n signal
N
Interval
(N + 1)