NEC 78K0 Series User Manual page 163

Table 6-5. CPU Clock Transition and SFR Register Setting Examples (2/4)
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(B) → (C) (X1 clock: 1 MHz ≤ f
(B) → (C) (external main clock: 1 MHz ≤ f
10 MHz)
(B) → (C) (X1 clock: 10 MHz < f
(B) → (C) (external main clock: 10 MHz < f
20 MHz)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET)).
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(B) → (D) (XT1 clock)
(B) → (D) (external subsystem clock)
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×:
CHAPTER 6 CLOCK GENERATOR
Note
AMPH
≤ 10 MHz)
0
XH
≤
0
XH
≤ 20 MHz)
1
XH
≤
1
XH
Unnecessary if these registers
XTSTART
0
1
0
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Don't care
Preliminary User's Manual U17260EJ3V1UD
EXCLK OSCSEL MSTOP
0 1 0
1 1 0
0 1 0
1 1 0
Unnecessary if the
are already set CPU is operating
with the high-speed
system clock
EXCLKS OSCSELS
0 1
× ×
1 1
Unnecessary if the CPU is operating
with the subsystem clock
Note
OSTC XSEL MCM0
Register
Must be 1 1
checked
1 1
Must not be
checked
Must be 1 1
checked
1 1
Must not be
checked
Waiting for CSS
Oscillation
Stabilization
Necessary 1
Unnecessary 1
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