I C Bus Definitions And Control Methods; Start Conditions - NEC 78K0 Series User Manual

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17.5 I C Bus Definitions and Control Methods
The following section describes the I
Figure 17-12 shows the transfer timing for the "start condition", "address", "data", and "stop condition" output via the
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I C bus's serial data bus.
SCL0
SDA0
Start
condition
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0's low
level period can be extended and a wait can be inserted.

17.5.1 Start conditions

A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level.
The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has
been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of
IICS0 is set (to 1).
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CHAPTER 17 SERIAL INTERFACE IIC0
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C bus's serial data communication format and the signals used by the I
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Figure 17-12. I C Bus Serial Data Transfer Timing
1-7 8 9 1-8
Address R/W ACK Data
Figure 17-13. Start Conditions
H
SCL0
SDA0
Preliminary User's Manual U17260EJ3V1UD
9 1-8 9
ACK Data ACK Stop
condition
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C bus.