NEC 78K0 Series User Manual page 520

(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Reset signal
Status of CPU
High-speed
system clock
(X1 oscillation)
(2) When internal high-speed oscillation clock is used as CPU clock
Reset signal
Status of CPU
Internal high-speed
oscillation clock
Remark f : X1 clock oscillation frequency
X
Table 21-4. Operation in Response to Interrupt Request in STOP Mode
Release Source
Maskable interrupt
request
Reset
×: don't care
520
CHAPTER 21 STANDBY FUNCTION
Figure 21-7. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Normal operation
(high-speed
STOP mode
system clock)
Oscillates Oscillation stopped
STOP
instruction
Normal operation
(internal high-speed
oscillation clock) STOP mode
Oscillation stopped
Oscillates
MK×× PR××
0
0
0
0
0
1
−
Preliminary User's Manual U17260EJ3V1UD
Reset
processing
Reset
µ
period (20 s (TYP.))
Oscillation Oscillation
stopped stopped
Oscillation stabilization time
Starting X1 oscillation is
specified by software.
Reset
processing
Reset
µ
period (20 s (TYP.))
Oscillation
stopped
Wait for oscillation
accuracy
stabilization
IE ISP
×
Next address
0 0
instruction execution
×
0 1 Interrupt servicing
execution
1 0 1 Next address
instruction execution
×
1 0
1 1 1 Interrupt servicing
execution
× × ×
STOP mode held
− × ×
Reset processing
Normal operation
(internal high-speed
oscillation clock)
Oscillates
11 16
(2 /f to 2 /f )
X X
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Operation