NEC 78K0 Series User Manual page 308

ADCE
Comparator
ADCS
Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be
µ
1 s or longer.
Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values
other than the identical data.
2. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is
operating on the subsystem clock and the peripheral hardware clock is stopped. For details,
see CHAPTER 31 CAUTIONS FOR WAIT.
308
CHAPTER 13 A/D CONVERTER
Figure 13-4. Timing Chart When Comparator Is Used
Comparator: 1/2AV
Conversion
operation
Note
Preliminary User's Manual U17260EJ3V1UD
operation
REF
Conversion Conversion
waiting operation
Conversion
stopped