Configuration Of Power-On-Clear Circuit; Operation Of Power-On-Clear Circuit - NEC 78K0 Series User Manual

23.2 Configuration of Power-on-Clear Circuit

The block diagram of the power-on-clear circuit is shown in Figure 23-1.
V
DD

23.3 Operation of Power-on-Clear Circuit

(1) In 1.59 V POC mode (option byte: POCMODE = 0)
• An internal reset signal is generated on power application.
detection voltage (V
POC
• The supply voltage (V
internal reset signal is generated. It is released when V
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
• An internal reset signal is generated on power application.
detection voltage (V
DDPOC
• The supply voltage (V
internal reset signal is generated. It is released when V
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is
shown below.
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
Figure 23-1. Block Diagram of Power-on-Clear Circuit
V
DD
+
−
Reference
voltage
source
= 1.59 V ±0.15 V), the reset status is released.
) and detection voltage (V
DD
= 2.7 V ±0.2 V), the reset status is released.
) and detection voltage (V
DD
Preliminary User's Manual U17260EJ3V1UD
Internal reset signal
When the supply voltage (V
= 1.59 V ±0.15 V) are compared. When V
POC
≥ V
.
DD POC
When the supply voltage (V
= 1.59 V ±0.15 V) are compared. When V
POC
≥ V
.
DD POC
) exceeds the
DD
< V , the
DD POC
) exceeds the
DD
< V , the
DD POC
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