NEC 78K0 Series User Manual page 587

Instruction
Mnemonic
Group
Bit AND1 CY, saddr.bit
manipulate
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
OR1 CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
XOR1 CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW. bit
CY, [HL].bit
SET1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CLR1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
SET1 CY
CLR1 CY
NOT1 CY
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 28 INSTRUCTION SET
Clocks
Operands Bytes
Note 1
3 6
−
3
2 4
−
3
2 6
3 6
−
3
2 4
−
3
2 6
3 6
−
3
2 4
−
3
2 6
2 4
−
3
2 4
−
2
2 6
2 4
−
3
2 4
−
2
2 6
1 2
1 2
1 2
Preliminary User's Manual U17260EJ3V1UD
Operation
Note 2
CY ← CY ∧ (saddr.bit)
7
CY ← CY ∧ sfr.bit
7
− CY ← CY ∧ A.bit
CY ← CY ∧ PSW.bit
7
CY ← CY ∧ (HL).bit
7
CY ← CY ∨ (saddr.bit)
7
CY ← CY ∨ sfr.bit
7
− CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
7
CY ← CY ∨ (HL).bit
7
CY ← CY ∨ (saddr.bit)
7
CY ← CY ∨ sfr.bit
7
− CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
7
CY ← CY ∨ (HL).bit
7
(saddr.bit) ← 1
6
sfr.bit ← 1
8
− A.bit ← 1
PSW.bit ← 1
6
(HL).bit ← 1
8
(saddr.bit) ← 0
6
sfr.bit ← 0
8
− A.bit ← 0
PSW.bit ← 0
6
(HL).bit ← 0
8
CY ← 1
−
− CY ← 0
− CY ← CY
) selected by the processor clock
CPU
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
× × ×
× × ×
1
0
×
587