NEC 78K0 Series User Manual page 524

Internal high-speed
oscillation clock
High-speed system clock
(when X1 oscillation is selected)
CPU clock
RESET
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Note Set P130 to high-level output by software.
Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 23
POWER-ON-CLEAR CIRCUIT and CHAPTER 24 LOW-VOLTAGE DETECTOR.
524
CHAPTER 22 RESET FUNCTION
Figure 22-4. Timing of Reset in STOP Mode by RESET Input
STOP instruction execution
Normal Stop status
operation (oscillation stop)
Delay
Preliminary User's Manual U17260EJ3V1UD
Wait for oscillation
accuracy
stabilization
Reset
processing
Reset period
(oscillation stop)
µ
(20 s (TYP.))
Delay
µ
(5 s (TYP.))
Hi-Z
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Note