NEC 78K0 Series User Manual page 174

(i) When CR00n is used as a compare register
The value set in CR00n is constantly compared with the TM0n count value, and an interrupt request signal
(INTTM00n) is generated if they match. The value is held until CR00n is rewritten.
(ii) When CR00n is used as a capture register
The count value of TM0n is captured to CR00n when a capture trigger is input.
As the capture trigger, an edge of a phase reverse to that of the TI00n pin or the valid edge of the TI01n pin
can be selected by using CRC0n or PRM0n.
Figure 7-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n)
Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011)
15
CR01n
(n = 0, 1)
(i) When CR01n is used as a compare register
The value set in CR01n is constantly compared with the TM0n count value, and an interrupt request signal
(INTTM01n) is generated if they match.
(ii) When CR01n is used as a capture register
The count value of TM0n is captured to CR01n when a capture trigger is input.
It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n pin valid edge is set
by PRM0n.
Cautions 1. To use this register as a compare register, set a value other than 0000H to CR00n and
CR01n.
2. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same
time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at
the same time. Select either of the functions.
3. If clearing of its 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n
(TMC0n) to 00 and input of the capture trigger conflict, then the captured data is undefined.
4. To change the mode from the capture mode to the comparison mode, first clear the TMC0n3
and TMC0n2 bits to 00, and then change the setting.
A value that has been once captured remains stored in CR00n unless the device is reset. If
the mode has been changed to the comparison mode, be sure to set a comparison value.
5. CR00n/CR01n does not perform the capture operation when it is set in the comparison
mode, even if a capture trigger is input to it.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
174
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
FF15H (CR010), FFB5H (CR011)
14 13 12 11 10
Preliminary User's Manual U17260EJ3V1UD
After reset: 0000H
FF14H (CR010), FFB4H (CR011)
9 8 7 6 5 4
R/W
3 2 1 0