NEC 78K0 Series User Manual page 341

8-bit single-chip microcontrollers
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(e) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data
reception, a reception error interrupt (INTSR0) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception
error interrupt (INTSR0) servicing (see Figure 14-3).
The contents of ASIS0 are cleared to 0 when ASIS0 is read.
Reception Error
Parity error
Framing error
Overrun error
(f) Noise filter of receive data
The R
D0 signal is sampled using the base clock output by the prescaler block.
X
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 14-10, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Base clock
R
D0/SI10/P11
X
CHAPTER 14 SERIAL INTERFACE UART0
Table 14-3. Cause of Reception Error
The parity specified for transmission does not match the parity of the receive data.
Stop bit is not detected.
Reception of the next data is completed before data is read from receive buffer
register 0 (RXB0).
Figure 14-10. Noise Filter Circuit
Internal signal A
In
Q
Match detector
Preliminary User's Manual U17260EJ3V1UD
Cause
In
Q
LD_EN
Internal signal B
341

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