NEC 78K0 Series User Manual page 419

8-bit single-chip microcontrollers
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Figure 17-6. Format of IIC Status Register 0 (IICS0) (3/3)
ACKD0
0
Acknowledge was not detected.
1
Acknowledge was detected.
Condition for clearing (ACKD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte's first clock
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
STD0
0
Start condition was not detected.
1
Start condition was detected. This indicates that the address transfer period is in effect.
Condition for clearing (STD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte's first clock following
address transfer
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
SPD0
0
Stop condition was not detected.
1
Stop condition was detected. The master device's communication is terminated and the bus is released.
Condition for clearing (SPD0 = 0)
• At the rising edge of the address transfer byte's first
clock following setting of this bit and detection of a start
condition
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Remark
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
Bit 7 of IIC control register 0 (IICC0)
(3) IIC flag register 0 (IICF0)
This register sets the operation mode of I
IICF0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are read-
only.
The IICRSV bit can be used to enable/disable the communication reservation function (see 17.5.14
Communication reservation).
STCEN can be used to set the initial value of the IICBSY bit (see 17.5.15 Other cautions).
IICRSV and STCEN can be written only when the operation of I
register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read.
Reset signal generation sets IICF0 to 00H.
CHAPTER 17 SERIAL INTERFACE IIC0
Detection of acknowledge (ACK)
Condition for setting (ACKD0 = 1)
• After the SDA0 line is set to low level at the rising edge of
SCL0's ninth clock
Detection of start condition
Condition for setting (STD0 = 1)
• When a start condition is detected
Detection of stop condition
Condition for setting (SPD0 = 1)
• When a stop condition is detected
2
C and indicates the status of the I
Preliminary User's Manual U17260EJ3V1UD
2
C bus.
2
C is disabled (bit 7 (IICE0) of IIC control
419

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