Setting Window Open Period Of Watchdog Timer - NEC 78K0 Series User Manual

11.4.3 Setting window open period of watchdog timer

Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option
byte (0080H). The outline of the window is as follows.
• If "ACH" is written to WDTE during the window open period, the watchdog timer is cleared and starts counting
again.
• Even if "ACH" is written to WDTE during the window close period, an abnormality is detected and an internal
reset signal is generated.
Example: If the window open period is 25%
Counting
starts
Window close period (75%)
Internal reset signal is generated
if ACH is written to WDTE.
Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the
overflow time regardless of the timing of the writing, and the watchdog timer starts counting
again.
The window open period to be set is as follows.
Table 11-4. Setting Window Open Period of Watchdog Timer
WINDOW1
0
0
1
1
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
2. The watchdog timer does not stop during self-programming of the flash memory and
298
CHAPTER 11 WATCHDOG TIMER
WINDOW0
0 25%
1 50%
0 75%
1 100%
is prohibited.
EEPROM emulation. During processing, the interrupt acknowledge time is delayed.
Set the overflow time and window size taking this delay into consideration.
Preliminary User's Manual U17260EJ3V1UD
Overflow
time
Window open
period (25%)
Counting starts again when
ACH is written to WDTE.
Window Open Period of Watchdog Timer