NEC 78K0 Series User Manual page 139

(2) Processor clock control register (PCC)
This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock.
PCC is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PCC to 01H.
Figure 6-3. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 01H
Symbol 7
PCC 0
CLS
0
1
CSS
0
1
Notes 1. Bit 5 is read-only.
2. XTSTART is used in combination with EXCLKS and OSCSELS (bits 5 and 4 of the Clock
Caution
Remarks 1. f
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KE2. Therefore, the relationship
between the CPU clock (f
CHAPTER 6 CLOCK GENERATOR
Note 1
R/W
6 <5>
Note2
XTSTART CLS
Main system clock
Subsystem clock
PCC2 PCC1
0 0
0 0
0 1
0 1
1 0
0 0
0 0
0 1
0 1
1 0
Other than above
operation mode select register (OSCCTL)). See (3) Setting of operation mode for
subsystem clock pin.
Be sure to clear bits 3 and 7 to 0.
: Main system clock oscillation frequency
XP
2. f : Subsystem clock oscillation frequency
SUB
) and the minimum instruction execution time is as shown in Table 6-2.
CPU
Preliminary User's Manual U17260EJ3V1UD
<4> 3 2
CSS 0 PCC2
CPU clock status
PCC0 CPU clock (f
0 f
XP
1 f /2 (default)
XP
2
0 f /2
XP
3
1 f /2
XP
4
0 f /2
XP
0 f /2
SUB
1
0
1
0
Setting prohibited
1 0
PCC1 PCC0
) selection
CPU
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