NEC 78K0 Series User Manual page 162

8-bit single-chip microcontrollers
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Table 6-5 shows transition of the CPU clock and examples of setting the SFR registers.
Table 6-5. CPU Clock Transition and SFR Register Setting Examples (1/4)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
Status Transition
(A) → (B)
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(A) → (B) → (C) (X1 clock: 1 MHz ≤ f
10 MHz)
(A) → (B) → (C) (external main clock: 1 MHz ≤
≤ 10 MHz)
f
XH
(A) → (B) → (C) (X1 clock: 10 MHz < f
20 MHz)
(A) → (B) → (C) (external main clock: 10 MHz <
≤ 20 MHz)
f
XH
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET)).
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(A) → (B) → (D) (XT1 clock)
(A) → (B) → (D) (external subsystem clock)
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×:
162
CHAPTER 6 CLOCK GENERATOR
SFR registers do not have to be set (default status after reset release).
AMPH
EXCLK
0
XH
0
1
XH
1
XTSTART
0
1
0
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Don't care
Preliminary User's Manual U17260EJ3V1UD
SFR Register Setting
OSCSEL
MSTOP
0
1
0
1
1
0
Must not be
0
1
0
1
1
0
Must not be
EXCLKS
OSCSELS
0
1
×
×
1
1
OSTC
XSEL
MCM0
Register
Must be
1
1
checked
1
1
checked
Must be
1
1
checked
1
1
checked
Waiting for
CSS
Oscillation
Stabilization
Necessary
1
Unnecessary
1

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