NEC 78K0 Series User Manual page 523

Internal high-speed
oscillation clock
High-speed system clock
(when X1 oscillation is selected)
CPU clock
RESET
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Note Set P130 to high-level output by software.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
Figure 22-3. Timing of Reset Due to Watchdog Timer Overflow
Internal high-speed
oscillation clock
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Watchdog timer
overflow
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Note Set P130 to high-level output by software.
Caution A watchdog timer internal reset resets the watchdog timer.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
CHAPTER 22 RESET FUNCTION
Figure 22-2. Timing of Reset by RESET Input
Reset period
Normal operation
(oscillation stop)
Delay
Normal operation
(oscillation stop)
Preliminary User's Manual U17260EJ3V1UD
Wait for oscillation
accuracy
stabilization
Reset
processing
µ
(20 s (TYP.))
Delay
µ
(5 s (TYP.))
Hi-Z
Wait for oscillation
accuracy
stabilization
Reset
processing
Reset period
µ
(20 s (TYP.))
Hi-Z
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Note
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Note
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