NEC 78K0 Series User Manual page 223

CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-46. Example of Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 0n (TMC0n)
0 0 0
(b) Capture/compare control register 0n (CRC0n)
0 0 0
(c) 16-bit timer output control register 0n (TOC0n)
OSPT0n OSPE0n
0 0 0
(d) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1
0 0 0
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
An interrupt signal (INTTM00n) is generated when the value of this register matches the count value of TM0n.
The count value of TM0n is not cleared.
(g) 16-bit capture/compare register 01n (CR01n)
An interrupt signal (INTTM01n) is generated when the value of this register matches the count value of TM0n.
The count value of TM0n is not cleared.
Caution Set values to CR00n and CR01n such that the condition 0000H < CR01n < CR00n ≤ FFFFH is
satisfied.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
TMC0n3 TMC0n2 TMC0n1
0 1 1
CRC0n2 CRC0n1 CRC0n0
0 0 0
TOC0n4 LVS0n LVR0n
1 0/1 0/1
ES0n0 3 2
0 0 0
Preliminary User's Manual U17260EJ3V1UD
OVF0n
0 0
Clears and starts on match
between TM0n and CR00n.
0 0
CR00n used as
compare register
CR01n used as
compare register
TOC0n1 TOE0n
1 1
Enables TO0n output
Specifies initial value of
TO0n output F/F
11: Inverts TO0n output on
match between TM0n
and CR00n/CR01n.
00: Disables one-shot pulse
output
PRM0n1 PRM0n0
0/1 0/1
Selects count clock
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