NEC 78K0 Series User Manual page 528

Table 22-2. Hardware Statuses After Reset Acknowledgment (3/3)
Serial interface IIC0 Shift register 0 (IIC0)
Control register 0 (IICC0)
Slave address register 0 (SVA0)
Clock selection register 0 (IICCL0)
Function expansion register 0 (IICX0)
Status register 0 (IICS0)
Flag register 0 (IICF0)
Note 2
Multiplier/divider Remainder data register 0 (SDR0)
Multiplication/division data register A0 (MDA0H, MDA0L)
Multiplication/division data register B0 (MDB0)
Multiplier/divider control register 0 (DMUC0)
Key interrupt Key return mode register (KRM)
Reset function Reset control flag register (RESF)
Low-voltage detector Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
Interrupt Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H)
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H)
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L,
PR1H)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2. Multiplier/divider is available only in the
3. These values vary depending on the reset source.
Reset Source
Register
RESF WDTRF bit
LVIRF bit
LVIM
LVIS
528
CHAPTER 22 RESET FUNCTION
Hardware
µ
PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D.
RESET Input Reset by POC
Cleared (0) Cleared (0)
Cleared (00H) Cleared (00H)
Preliminary User's Manual U17260EJ3V1UD
Status After Reset
Acknowledgment
00H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
Reset by WDT Reset by LVI
Set (1) Held
Held Set (1)
Cleared (00H) Held
Note 1
Note 3
Note 3
Note 3