Cautions For 16-Bit Timer/Event Counters 00 And 01 - NEC 78K0 Series User Manual

7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01

(1) Restrictions for each channel of 16-bit timer/event counter 0n
Table 7-5 shows the restrictions for each channel.
Table 7-5. Restrictions for Each Channel of 16-Bit Timer/Event Counter 0n
Operation
As interval timer
As square wave output
As external event counter
As clear & start mode entered by
TI00n pin valid edge input
As free-running timer
As PPG output
As one-shot pulse output
As pulse width measurement
(2) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because counting TM0n is started asynchronously to the count pulse.
TM0n count value
(3) Setting of CR00n and CR01n (clear & start mode entered upon a match between TM0n and CR00n)
Set a value other than 0000H to CR00n and CR01n (TM0n cannot count one pulse when it is used as an external
event counter).
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
TOC0n = 00H
Using timer output (TO0n) is prohibited when detection of the valid edge of the TI01n pin is
used.
TOC0n = 00H
Setting identical values or 0000H to CR00n and CP01n is prohibited.
TOC0n = 00H
Figure 7-60. Start Timing of TM0n Count
Count pulse
0000H
Timer start
Preliminary User's Manual U17260EJ3V1UD
Restriction
−
−
−
0001H 0002H 0003H 0004H
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