NEC 78K0 Series User Manual page 545

Figure 24-6. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Detects Level of Input Voltage from External Input Pin (EXLVI))
Input voltage from
external input pin (EXLVI)
LVI detection voltage
(V )
EXLVI
LVIMK flag
H
(set by software)
LVISEL flag
(set by software)
LVION flag
(set by software)
LVIF flag
LVIMD flag
(set by software)
Note 3
LVIRF flag
LVI reset signal
Internal reset signal
Notes 1. The LVIMK flag is set to "1" by reset signal generation.
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22
RESET FUNCTION.
Remark <1> to <6> in Figure 24-6 above correspond to <1> to <6> in the description of "When starting
operation" in 24.4.1 (2) When detecting level of input voltage from external input pin (EXLVI).
CHAPTER 24 LOW-VOLTAGE DETECTOR
Note 1
<1>
Not cleared
<2>
Not cleared
<3>
<4> Wait time
<5>
Note 2
Not cleared
<6>
Cleared by
software
Preliminary User's Manual U17260EJ3V1UD
Not cleared
Not cleared
Not cleared
Cleared by
software
Time
Not cleared
Not cleared
Not cleared
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