(When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3)
(3) Stop condition
Processing by master device
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
Transfer lines
SCL0
SDA0
Processing by slave device
IIC0
ACKD0
STD0
SPD0
WTIM0
H
ACKE0
H
MSTS0
L
STT0
L
SPT0
L
WREL0
INTIIC0
TRC0
Note To cancel master wait, write "FFH" to IIC0 or set WREL0.
476
CHAPTER 17 SERIAL INTERFACE IIC0
Figure 17-28. Example of Slave to Master Communication
← FFH
IIC0
Note
Note
1
2
3
4
5
D7
D6
D5
D4
D3
←
IIC0
data
Preliminary User's Manual U17260EJ3V1UD
6
7
8
9
D2
D1
D0
NACK
←
IIC0
address
(When SPIE0 = 1)
1
AD6
Stop
Start
condition
condition
(When SPIE0 = 1)