Lse Clock; Lsi Clock; System Clock (Sysclk) Selection - ST STM32F101 Series Reference Manual

Reset and clock control (RCC)
If the USB interface is used in the application, the PLL must be programmed to output 48 or
72 MHz. This is needed to provide a 48 MHz USBCLK.
4.2.4

LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in
register (RCC_BDCR).
The LSERDY flag in the
crystal is stable or not. At startup, the LSE crystal output clock signal is not released until
this bit is set by hardware. An interrupt can be generated if enabled in the
register (RCC_CIR).
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency of
32.768 kHz. You select this mode by setting the LSEBYP and LSEON bits in the
domain control register
with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be
left Hi-Z. See
4.2.5

LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto Wakeup unit (AWU). The
clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to
the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the
(RCC_CSR).
The LSIRDY flag in the
internal oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the
(RCC_CIR).
4.2.6

System clock (SYSCLK) selection

After a system Reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source will be ready. Status bits in the
control register (RCC_CR)
used as system clock.
52/501
Backup domain control register (RCC_BDCR)
(RCC_BDCR). The external clock signal (square, sinus or triangle)
Figure 8.
Control/status register (RCC_CSR)
indicate which clock(s) is (are) ready and which clock is currently
Backup domain control
indicates if the LSE
Clock interrupt
Control/status register
indicates if the low-speed
Clock interrupt register
RM0008
Backup
Clock